AS4C64M32MD2-25BCN datasheet(40/129 Pages) ALSC

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Figure 4.23 — LPDDR2-SX: Burst write followed by precharge: WL = 1, BL = 4

4.8.3

LPDDR2-SX: Auto Precharge operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or

the auto-precharge function. When a Read or a Write command is given to the LPDDR2 SDRAM, the AP bit (CA0f) may be set to

allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle.

If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed and

the bank remains active at the completion of the burst.

If AP is HIGH when the Read or Write command is issued, then the auto-precharge function is engaged. This feature

allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon Read or

Write latency) thus improving system performance for random data access.

4.8.3.1

LPDDR2-SX: Burst Read with Auto-Precharge

If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged.

LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 +

RU(tRTP/tCK) clock cycles later than the Read with AP command, whichever is greater. Refer to Table 9 for equations

related to Auto-Precharge for LPDDR2-S4.

A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied

simultaneously.

The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Figure 4.24 — LPDDR2-S4: Burst read with Auto-Precharge:

RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2

4.8.3.2

LPDDR2-SX: Burst write with Auto-Precharge

If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The

LPDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is tWR cycles after the completion of

the burst write.

A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied.

The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

The RAS cycle time (tRC) from the previous bank activation has been satisfied.

AS4C64M32MD2-25BCN

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AS4C64M32MD2-25BCN Datasheet(PDF) 40 Page - Alliance Semiconductor Corporation