AS4C64M32MD2-25BCN datasheet(83/129 Pages) ALSC

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Table 27 — Allowed time before ring back (tDVAC) for CK - CK# and DQS - DQS#

Slew Rate [V/ns]

tDVAC [ps]

@|VIH/Ldiff(ac)| =440mV

@|VIH/Ldiff(ac)| =600mV

Min

>4.0

175

4.0

170

3.0

167

2.0

163

1.8

162

1.6

161

1.4

159

1.2

155

1.0

150

<1.0

150

7.4.3

Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, CK#, or DQS#) has also to comply with certain

requirements for single-ended signals.

CK and CK# shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle.

DQS, DQS# shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid transition.

Note that the applicable ac-levels for CA and DQ’s are different per speed-bin.

Figure 7.5 — Single-ended requirement for differential signals.

Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential

signals have a requirement with respect to VDDQ/2 for DQS, DQS# and VDDCA/2 for CK, CK#; this is nominally the

same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended

components of differential signals the requirement to reach VSEL(AC)max, VSEH(AC)min has no bearing on timing,

but adds a restriction on the common mode characteristics of these signals.

The Single-ended requirements for CK, CK#, DQS, and DQS# are found in tables 23 and Single-ended AC and DC

Input Levels for DQ and DM in tables 25, respectively.

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

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Rev.1.0 July 2016

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