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AS4C64M32MD2-25BCN Datasheet(PDF) 86 Page - Alliance Semiconductor Corporation

Part # AS4C64M32MD2-25BCN
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
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AS4C64M32MD2-25BCN Datasheet(HTML) 86 Page - Alliance Semiconductor Corporation

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7.6 Slew Rate Definitions for Single-Ended Input Signals
See “CA and CS# Setup, Hold and Derating” for single-ended slew rate definitions for address and command signals.
See “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals.
7.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in
Table 30 and Figure 7.7.
Table 30 — Differential Input Slew Rate Definition
Description
Measured
Defined by
from
to
Differential input slew rate for rising edge
VILdiffmax
VIHdiffmin
[VIHdiffmin - VILdiffmax] / DeltaTRdiff
(CK - CK# and DQS - DQS#)
Differential input slew rate for falling edge
VIHdiffmin
VILdiffmax
[VIHdiffmin - VILdiffmax] / DeltaTFdiff
(CK - CK# and DQS - DQS#)
NOTE 1 The differential signal (i.e. CK - CK# and DQS - DQS# ) must be linear between these thresholds
Figure 7.7 — Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
AS4C64M32MD2-25BCN
AS4C128M16MD2-25BCN
Confidential
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Rev.1.0 July 2016



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