AS4C64M32MD2-25BCN datasheet(32/129 Pages) ALSC

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the Burst Length (BL). Minimum read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 - WL clock cycles. Note

that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated read

burst should be used as “BL” to calculate the minimum read to write delay.

Figure 4.12 — LPDDR2-SX: Seamless burst read: RL = 3, BL = 4, tCCD = 2

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation,

every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation.

For LPDDR2-SDRAM, this operation is allowed regardless of whether the accesses read the same or different banks

as long as the banks are activated.

4.4.1

Reads interrupted by a read

For LPDDR2-S4 burst read can be interrupted by another read on even clock cycles after the Read command,

provided that tCCD is met

Figure 4.13 — LPDDR2-SX: Read burst interrupt example: RL = 3, BL = 8, tCCD = 2

NOTE 1 For LPDDR2-S4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16.

NOTE 2 For LPDDR2-S4 devices, read burst interrupt may only occur on even clock cycles after the previous commands, provided that tCCD is

met.

NOTE 3 Reads can only be interrupted by other reads or the BST command.

NOTE 4 Read burst interruption is allowed to any bank inside DRAM.

NOTE 5 Read burst with Auto-Precharge is not allowed to be interrupted

NOTE 6 The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read.

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AS4C64M32MD2-25BCN Datasheet(PDF) 32 Page - Alliance Semiconductor Corporation