AS4C64M32MD2-25BCN datasheet(33/129 Pages) ALSC

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4.5 Burst Write Operation

The Burst Write command is initiated by having CS# LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge of

the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for

the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is issued

to the rising edge of the clock from which the tDQSS delay is measured. The first valid datum shall be driven WL * tCK

+ tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe signal (DQS)

should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied to the DQ pins

tDS prior to the respective edge of the DQS, DQS# and held valid until tDH after that edge. The burst data are

sampled on successive edges of the DQS, DQS# until the burst length is completed, which is 4, 8, or 16 bit burst.

For LPDDR2-SDRAM devices, tWR must be satisfied before a precharge command to the same bank may be issued

after a burst write operation.

Input timings are measured relative to the crosspoint of DQS and its complement, DQS#.

Figure 4.14: Data Input (WRITE) Timing

Transitioning data

CK#

CA[9:0]

CMD

DQS#

DQS

Tx+1

Ty+1

WL = 1

DQS#

DQS

DIN

Case 1: tDQSSmax

Case 2: tDQSSmin

tDQSSmax

tDSS

Completion of burst WRITE

tWR

tRP

tDQSSmin

tDSH

Figure 4.15 — LPDDR2-SX: Burst write : WL = 1, BL = 4

AS4C64M32MD2-25BCN

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AS4C64M32MD2-25BCN Datasheet(PDF) 33 Page - Alliance Semiconductor Corporation