AS4C64M32MD2-25BCN datasheet(37/129 Pages) ALSC

Electronic Components Datasheet Search

ALLDATASHEET.CO.NZ

AS4C64M32MD2-25BCN Datasheet(PDF) 37 Page - Alliance Semiconductor Corporation

Part #	AS4C64M32MD2-25BCN

Description	Deep Power Down Mode

PDF	129 Pages

Scroll/Zoom	100%

Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

Logo

37 / 129 page

4.7 Write Data Mask

One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the

implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given

cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is

internally loaded identically to data bits to insure matched system timing.

Data Mask Timing

Data Mask Function, WL = 2, BL = 4 shown, second DQ masked

Figure 4.20 — LPDDR2-SX: Write data mask

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

- 37/129 -

Rev.1.0 July 2016

Does ALLDATASHEET help your business so far? [ DONATE ]
About Alldatasheet \| Advertisement \| Contact us \| Privacy Policy \| Link to Datasheet \| Link Exchange \| Manufacturer List All Rights Reserved©Alldatasheet.com
Mirror Sites English : Alldatasheet.com \| English : Alldatasheet.net \| Chinese : Alldatasheetcn.com \| German : Alldatasheetde.com \| Japanese : Alldatasheet.jp Russian : Alldatasheetru.com \| Korean : Alldatasheet.co.kr \| Spanish : Alldatasheet.es \| French : Alldatasheet.fr \| Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com \| Polish : Alldatasheet.pl \| Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in \| Mexican : Alldatasheet.com.mx \| British : Alldatasheet.co.uk \| New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com \| icmetro.com

Does ALLDATASHEET help your business so far? [ DONATE ]

Family Site : ic2ic.com | icmetro.com