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AS4C64M32MD2-25BCN Datasheet(PDF) 22 Page - Alliance Semiconductor Corporation |
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AS4C64M32MD2-25BCN Datasheet(HTML) 22 Page - Alliance Semiconductor Corporation |
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22 / 129 page  NOTE 5 LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration command. NOTE 6 Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. MR11:15_(Reserved) (MA<7:0> = 0BH-0FH): MR16_PASR_Bank Mask (MA<7:0> = 010H): S2 and S4 SDRAM only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 S4 SDRAM Bank Mask (4-bank or 8 bank) S4 SDRAM : Bank <7:0> Mask Write- only OP<7:0> 0B: refresh enable to the bank (=unmasked, default) 1 1B: refresh blocked (=masked) 1. For 4-bank S4 SDRAM, only<3:0> are used. OP Bank Mask 4-Bank S4 SDRAM 8-Bank S4 SDRAM 0 XXXX XXX1 Bank 0 Bank 0 1 XXXX XX1X Bank 1 Bank 1 2 XXXX X1XX Bank 2 Bank 2 3 XXXX 1XXX Bank 3 Bank 3 4 XXX1 XXXX - Bank 4 5 XX1X XXXX - Bank 5 6 X1XX XXXX - Bank 6 7 1XXX XXXX - Bank 7 MR17_PASR_Segment Mask (MA<7:0> = 011H): 1Gb ~ 8Gb S4 SDRAM only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment Mask Segment <7:0> Mask Write- only OP<7:0> 0B: refresh enable to the segment (=unmasked, default) 1B: refresh blocked (=masked) 1Gb 2Gb, 4Gb 8Gb Segment OP Segment Mask R12 : 10 R13 : 11 R14 : 12 0 0 XXXX XXX1 000B 1 1 XXXX XX1X 001B 2 2 XXXX X1XX 010B 3 3 XXXX 1XXX 011B 4 4 XXX1 XXXX 100B 5 5 XX1X XXXX 101B 6 6 X1XX XXXX 110B 7 7 1XXX XXXX 111B NOTE This table indicates the range of row addresses in each masked segment X is do not care for a particular segment MR18-19_Reserved (MA<7:0> = 012H - 013H): MR20-31_Do Not Use, NVM only MR32_DQ Calibration Pattern A (MA<7:0> = 20H): Reads to MR32 return DQ Calibration Pattern “A”. See “DQ Calibration” MR33:39_(Do Not Use) (MA<7:0> = 21H-27H): MR40_DQ Calibration Pattern B (MA<7:0> = 28H): Reads to MR40 return DQ Calibration Pattern “B”. See “DQ Calibration”. AS4C64M32MD2-25BCN AS4C128M16MD2-25BCN Confidential - 22/129 - Rev.1.0 July 2016 |
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