AS4C64M32MD2-25BCN datasheet(56/129 Pages) ALSC

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4.12

Mode Register Write Command

The Mode Register Write command is used to write configuration data to mode registers.

The Mode Register Write (MRW) command is initiated by having CS# LOW, CA0 LOW, CA1 LOW, CA2 LOW, and

CA3 LOW at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be

written to the mode register is contained in CA9f-CA2f. The MRW command period is defined by tMRW. Mode

Figure 4.39 — Mode Register Write timing example: RL = 3, tMRW = 5

NOTE 1 The Mode Register Write Command period is tMRW. No command (other than Nop) is allowed during this period.

NOTE 2 At time Ty, the device is in the idle state.

4.12.1 LPDDR2-SX: Mode Register Write

For LPDDR2-S devices, the MRW may only be issued when all banks are in the idle precharge state. One method of

ensuring that the banks are in the idle precharge state is to issue a Precharge-All command.

4.12.2 Mode Register Write Reset (MRW Reset)

Any MRW command issued to MRW63 initiates an MRW Reset. The MRW Reset command brings the device to the

Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence. The MRW Reset command may

be issued from the Idle state for LPDDR2-SX devices. This command resets all Mode Registers to their default values..

No commands other than NOP may be issued to the LPDDR2 device during the MRW Reset period (tINIT4). After

MRW Reset, boot timings must be observed until the device initialization sequence is complete and the device is in the

Idle state. Array data for LPDDR2-SX devices are undefined after the MRW Reset command.

For the timing diagram related to MRW Reset.

4.12.3 Mode Register Write ZQ Calibration Command

The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to

calibrate the LPDDR2 ouput drivers (RON) over process, temperature, and voltage. LPDDR2-S4 devices support ZQ

Calibration.

There are four ZQ Calibration commands and related timings, tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT

corresponds to the initialization calibration, tZQRESET for resetting ZQ setting to default, tZQCL is for long calibration,

and tZQCS is for short calibration. See Mode Register 10 for description on the command codes for the different ZQ

Calibration commands.

The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 devices. This Initialization Calibration

achieves a RON accuracy of +/-15%. After initialization, the ZQ Long Calibration may be used to re-calibrate the

system to a RON accuracy of +/-15%. A ZQ Short Calibration may be used periodically to compensate for temperature

and voltage drift in the system.

The ZQReset Command resets the RON calibration to a default accuracy of +/-30% across process, voltage, and

temperature. This command is used to ensure RON accuracy to +/-30% when ZQCS and ZQCL are not used.

One ZQCS command can effectively correct a minimum of 1.5% (ZQCorrection) of RON impedance error within

tZQCS for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature

Sensitivity’. The appropriate interval between ZQCS commands can be determined from these tables One method for

calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates

that the LPDDR2 is subject to in the application, is illustrated. The interval could be defined by the following formula:

where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage sensitivities.

For example, if TSens = 0.75% / oC, VSens = 0.20% / mV, Tdriftrate = 1 oC / sec and

Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as

AS4C64M32MD2-25BCN

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