AS4C64M32MD2-25BCN datasheet(34/129 Pages) ALSC

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Figure 4.16 — LPDDR2-SX: Burst write followed by burst read: RL=3, WL = 1, BL = 4

NOTE 1 The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 +

RU( tWTR/tCK)].

NOTE 2 tWTR starts at the rising edge of the clock after the last valid input datum.

NOTE 3 If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst should be

used as “BL” to calculate the minimum write to read delay.

4.5.1

Writes interrupted by a write

For LPDDR2-S4 devices, burst write can only be interrupted by another write on even clock cycles after the Write

command, provided that tCCD(min) is met.

Figure 4.17 — LPDDR2-SX: Write burst interrupt timing: WL = 1, BL = 8, tCCD = 2

NOTE 1 For LPDDR2-S4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16.

NOTE 2 For LPDDR2-S4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided that

tCCD(min) is met.

NOTE 3 Writes can only be interrupted by other writes or the BST command.

NOTE 4 Write burst interruption is allowed to any bank inside DRAM.

NOTE 5 Write burst with Auto-Precharge is not allowed to be interrupted

NOTE 6 The effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting

write.

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

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AS4C64M32MD2-25BCN Datasheet(PDF) 34 Page - Alliance Semiconductor Corporation