AS4C64M32MD2-25BCN datasheet(43/129 Pages) ALSC

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4.9 LPDDR2-SX: Refresh command

The Refresh command is initiated by having CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of

clock. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of clock and All Bank Refresh is initiated by

having CA3 HIGH at the rising edge of clock. Per Bank Refresh is only allowed in devices with 8 banks. A Per Bank

Refresh command, REFpb performs a refresh operation to the bank which is scheduled by the bank counter in the

memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: “0-1- 2-3-4-5-6-7-0-1-

...”. The bank count is synchronized between the controller and the SDRAM upon issuing a RESET command or at

every exit from self refresh, by resetting bank count to zero. The bank addressing for the Per Bank Refresh count is

the same as established in the single-bank Precharge command (see Table 8 , “Bank selection for Precharge by

address bits”).

A bank must be idle before it can be refreshed. It is the responsibility of the controller to track the bank being refreshed

by the Per Bank Refresh command.

As shown in Table 10, the REFpb command may not be issued to the memory until the following conditions are met:

a) tRFCab has been satisified after the prior REFab command

b) tRFCpb has been satisfied after the prior REFpb command

c) tRP has been satisified after the prior Precharge command to that given bank

tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a

different bank than affected by the REFpb command).

The target bank is inaccessable during the Per Bank Refresh cycle time (tRFCpb), however other banks within the

device are accessable and may be addressed during the Per Bank Refresh cycle. During the REFpb operation, any of

the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write

command.

When the Per Bank refresh cycle has completed, the affected bank will be in the Idle state.

As shown in Table 10, after issuing REFpb:

a) tRFCpb must be satisified before issuing a REFab command

b) tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank

c) tRRD must be satisified before issuing an ACTIVATE command to a different bank

d) tRFCpb must be satisified before issuing another REFpb command

An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in Idle state

when REFab is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count

between the controller and the SDRAM to zero.

As shown in Table 10, the REFab command may not be issued to the memory until the following conditions have been

met:

a) tRFCab has been satisified after the prior REFab command

b) tRFCpb has been satisified after the prior REFpb command

c) tRP has been satisified after prior Precharge commands

When the All Bank refresh cycle has completed, all banks will be in the Idle state.

As shown in Table 10, after issuing REFab:

a) the tRFCab latency must be satisfied before issuing an ACTIVATE command

b) the tRFCab latency must be satisfied before issuing a REFab or REFpb command.

AS4C64M32MD2-25BCN

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