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AS4C64M32MD2-25BCN Datasheet(PDF) 42 Page - Alliance Semiconductor Corporation |
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AS4C64M32MD2-25BCN Datasheet(HTML) 42 Page - Alliance Semiconductor Corporation |
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42 / 129 page  Table 9 – LPDDR-S4 : Precharge & Auto Precharge Clarification From To command Minimum Delay between unit Notes command " From Command " to "To Command " Read Precharge (to same Bank as Read) BL/2 + max(2,RU(tRTP/tCK)) - 2 clks 1 Precharge All BL/2 + max(2,RU(tRTP/tCK)) - 2 clks 1 BST Precharge (to same Bank as Read) 1 clks 1 (For Reads) Precharge All 1 clks 1 Read w/AP Precharge (to same Bank as Read w/AP) BL/2 + max(2,RU(tRTP/tCK)) - 2 clks 1.2 Precharge All BL/2 + max(2,RU(tRTP/tCK)) - 2 clks 1 Activate (to same Bank as Read w/AP) BL/2 + max(2,RU(tRTP/tCK)) - 2 + RU(tRPpb/tCK) clks 1 Write or Write w/AP (same bank) Illegal clks 3 Write or Write w/AP (different bank) RL+BL/2+RU(tDQSCKmax/tCK) - WL+1 clks 3 Read or Read w/AP (same bank) Illegal clks 3 Read or Read w/AP (different bank) BL/2 clks 3 Write Precharge (to same Bank as Write) WL + BL/2 + RU(tWR/tCK)+1 clks 1 Precharge All WL + BL/2 + RU(tWR/tCK)+1 clks 1 BST Precharge (to same Bank as Write) WL + RU(tWR/tCK)+1 clks 1 (For Writes) Precharge All WL + RU(tWR/tCK)+1 clks 1 Write w/AP Precharge (to same Bank as Write w/AP) WL + BL/2 + RU(tWR/tCK)+1 clks 1 Precharge All WL + BL/2 + RU(tWR/tCK)+1 clks 1 Activate (to same Bank as Write w/AP) WL + BL/2 + RU(tWR/tCK)+1 +RU(tRPpb/tCK) clks 1 Write or Write w/AP (same bank) Illegal clks 3 Write or Write w/AP (different bank) BL/2 clks 3 Read or Read w/AP (same bank) Illegal clks 3 Read or Read w/AP (different bank) W/L + BL/2 + RU(tWTR/tCK)+1 clks 3 Precharge Precharge (to same Bank as Precharge) 1 clks 1 Precharge All 1 clks 1 Precharge All Precharge 1 clks 1 Precharge All 1 clks 1 NOTE 1 For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank, NOTE 2 Any command issued during the minimum delay time as specified in Table 51 is illegal. NOTE 3 After Read With AP, seamless read operations to different banks are supported. After Write with AP, seamless write operation to different banks are supported. Read w/AP and Write w/AP may not be interrupted or truncated. AS4C64M32MD2-25BCN AS4C128M16MD2-25BCN Confidential - 42/129 - Rev.1.0 July 2016 |
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