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AS4C64M32MD2-25BCN Datasheet(PDF) 31 Page - Alliance Semiconductor Corporation

Part # AS4C64M32MD2-25BCN
Description  Deep Power Down Mode
PDF  129 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C64M32MD2-25BCN Datasheet(HTML) 31 Page - Alliance Semiconductor Corporation

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CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
Transitioning data
RL = 5
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
Tn+7
Tn+8
tDQSCKn
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
A0
160ns maximum...
1
DOU
A
RL = 5
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+8
tDQSCKm
DOUT
A0
DOUT
A1
DOUT
A2
DOUT
A3
1
...160ns maximum
DOUT
A0
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
A0
DOUT
A1
DOUT
A2
DOUT
A0
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
A2
DOUT
A3
DOUT
A3
Figure 4.10 — LPDDR2: tDQSCKDS timing
NOTE 1 tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn,tDQSCKm} pair for reads within
a consecutive burst within any 160ns rolling window.
Figure 4.11 — LPDDR2-SX: Burst read followed by burst write: RL = 3, WL = 1, BL = 4
The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL) and
AS4C64M32MD2-25BCN
AS4C128M16MD2-25BCN
Confidential
- 31/129 -
Rev.1.0 July 2016



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