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4.14

LPDDR2-SX: Deep Power-Down

Deep Power-Down is entered when CKE is registered LOW with CS# LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at

the rising edge of clock. A NOP command must be driven in the clock cycle following the power-down command. CKE

is not allowed to go LOW while mode register, read, or write operations are in progress.

All banks must be in idle state with no activity on the data bus prior to entering the Deep Power Down mode. During

Deep Power-Down, CKE must be held LOW.

In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry

may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep Power-

Down. VrefDQ and VrefCA may be at any level within minimum and maximum levels (see “Absolute Maximum DC

Ratings”). However prior to exiting Deep Power-Down, Vref must be within specified limits ( See “Recommended DC

Operating Conditions” ).

The contents of the SDRAM may be lost upon entry into Deep Power-Down mode.

The Deep Power-Down state is exited when CKE is registered HIGH, while meeting tISCKE with a stable clock input.

The SDRAM must be fully re-initialized as described in the Power up initialization Sequence. The SDRAM is ready for

normal operation after the initialization sequence

CK#

CKE

CS#

CMD NOP

Enter

DPD

NOP

Exit

DPD

NOP

RESET

tISCKE

tDPD

tIHCKE

Enter DPD mode

Exit DPD mode

Input clock frequency can be changed

or clock can be stopped during self DPD.

Don

＇t care

tRP

2 tCK (MIN)

tINIT3

Figure 4.56 — LPDDR2-SX: Deep power down entry and exit timing diagram

NOTE 1 Initialization sequence may start at any time after Tc.

NOTE 2 tINIT3, and Tc refer to timings in the LPDDR2 initialization sequence. For more detail, see 3.4.

NOTE 3 Input clock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep power-

down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to deep power-down exit and the clock frequency is

between the minimum and maximum frequency for the particular speed grade.

AS4C64M32MD2-25BCN

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