AS4C64M32MD2-25BCN datasheet(12/129 Pages) ALSC

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devices which do not support the ZQ Calibration command, this command shall be ignored. This command is used to

calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature. Optionally, the MRW ZQ

Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in which more than one

LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration commands. The device is

ready for normal operation after tZQINIT.

6. Normal Operation:

After tZQINIT (Tg), MRW commands shall be used to properly configure the memory, for example the output buffer

driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target

frequency and memory configuration.

The LPDDR2 device will now be in IDLE state and ready for any valid command.

After Tg, the clock frequency may be changed according to the clock frequency change procedure described in

section “Input clock stop and frequency change” of this specification.

Table 1 – Timing Parameters for initialization

Symbol

Value

Unit

Comment

min

max

tINIT0

Maximum Power Ramp Time

tINIT1

100

Minimum CKE low time after completion of power ramp

tINIT2

tCK

Minimum stable clock before first CKE high

tINIT3

200

Minimum Idle time after first CKE assertion

tINIT4

Minimum Idle time after Reset command

tINIT5

Maximum duration of Device Auto-Initialization

tZQINIT

ZQ Initial Calibration for LPDDR2-S4 devices

tCKb

100

Clock cycle time during boot

CK/CK#

CKE

RTT

Supplies

RESET

MRR

tINIT2

tINIT0

tINIT1

tINIT3

tISCKE

tINIT5

tINIT4

tZQINIT

Figure 3.2 Power Ramp and Initialization Sequence

3.2.2 Initialization after Reset (without Power ramp):

If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall begin

with step 3 (Td).

3.2.3 Power-off Sequence

The following sequence shall be used to power off the LPDDR2 device. Unless specified otherwise, these steps are

mandatory and apply to S4 devices.

While removing power, CKE shall be held at a logic low level (=< 0.2 x VDD2), all other inputs shall be between

VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is

held low. DQ, DM, DQS, and DQS# voltage levels must be between VSSQ and VDDQ during power off sequence to

avoid latch-up. CK, CK#, CS#, and CA input levels must be between VSSCA and VDD2 during power off sequence to

avoid latch-up.

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

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