AS4C64M32MD2-25BCN datasheet(39/129 Pages) ALSC

39 / 129 page

Figure 4.21 — LPDDR2-S4: Burst read followed by Precharge:

RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2

Figure 4.22 — LPDDR2-S4: Burst read followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3

4.8.2

LPDDR2-SX: Burst Write followed by Precharge

For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge command

may be issued. This delay is known as the write recovery time (tWR) referenced from the completion of the burst write

to the precharge command. No Precharge command to the same bank should be issued prior to the tWR delay.

LPDDR2-S4 devices write data to the array in prefetch quadruples (prefetch = 4). The beginning of an internal write

operation may only begin after a prefetch group has been latched completely. Therefore, the write recovery time (tWR)

starts at different boundaries for LPDDR2-S4 devices.

For LPDDR2-S4 devices, minimum Write to Precharge command spacing to the same bank is WL + BL/2 + 1 +

RU(tWR/tCK) clock cycles. For an untruncated burst, BL is the value from the Mode Register. For an truncated burst,

BL is the effective burst length.

See Table 9 for Write to Precharge timings for LPDDR2-S4

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

- 39/129 -

Rev.1.0 July 2016

AS4C64M32MD2-25BCN Datasheet(PDF) 39 Page - Alliance Semiconductor Corporation