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AS4C64M32MD2-25BCN Datasheet(PDF) 17 Page - Alliance Semiconductor Corporation |
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AS4C64M32MD2-25BCN Datasheet(HTML) 17 Page - Alliance Semiconductor Corporation |
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17 / 129 page  MR1 Device Feature 1 (MA <7:0> =01H) : OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 nWR (for AP) WC BT BL BL Write-only OP<2:0> 010B: BL4 (default) 011B: BL8 110B: BL16 All others : reserved BT Write-only OP<3> 0B: Sequential (default) 1 1B: Interleaved WC Write-only OP<4> 0B: Wrap (default) 1B: No wrap (allowed for SDRAM BL4 only) nWR Write-only OP<7:5> 001B: nWR =3(default) 010B: nWR =4 011B: nWR =5 100B: nWR =6 101B: nWR =7 110B :nWR =8 All others : reserved 2 NOTE 1 BL 16, interleaved is not an official combination to be supported. NOTE 2 Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK). AS4C64M32MD2-25BCN AS4C128M16MD2-25BCN Confidential - 17/129 - Rev.1.0 July 2016 |
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