AS4C64M32MD2-25BCN datasheet(57/129 Pages) ALSC

57 / 129 page

For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all

banks precharged.

No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT, tZQCL, tZQCS).

The quiet time on the LPDDR2 data bus helps to accurately calibrate RON. There is no required quiet time after the

ZQ Reset command. If multiple devices share a single ZQ Resistor, only one device may be calibrating at any given

time. After calibration is achieved, the LPDDR2 device shall disable the ZQ ball’s current consumption path to reduce

power.

In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQCS, or

tZQCL between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be

connected permanently to VDD2. In this case, the LPDDR2 device shall ignore ZQ calibration commands and the

device will use the default calibration settings ( See “Output Driver DC Electrical Characteristics without ZQ

Calibration”)

Figure 4.40 — ZQ Calibration Initialization timing example

NOTE 1: The ZQ Calibration Initialization period is tZQINIT. No command (other than Nop) is allowed during this period.

NOTE 2: CKE must be continuously registered HIGH during the calibration period.

NOTE 3: All devices connected to the DQ bus should be high impedance during the calibration process.

Figure 4.41 — ZQ Calibration Short timing example

NOTE 1: The ZQ Calibration Short period is tZQCS. No command (other than Nop) is allowed during this period.

NOTE 2: CKE must be continuously registered HIGH during the calibration period.

NOTE 3: All devices connected to the DQ bus should be high impedance during the calibration process.

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

- 57/129 -

Rev.1.0 July 2016

AS4C64M32MD2-25BCN Datasheet(PDF) 57 Page - Alliance Semiconductor Corporation