AS4C64M32MD2-25BCN datasheet(20/129 Pages) ALSC

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NOTE 3 If OP2 equals ‘1’, the device temperature is greater than 85℃

NOTE 4 OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4.

NOTE 5 LPDDR2 might not operate properly when OP[2:0] = 000B or 111B.

NOTE 6 LPDDR2-SX devices shall be de-rated by adding 1.875 ns to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD.

tDQSCK shall be de-rated according to the tDQSCK de-rating in Table 52. Prevailing clock frequency spec and related setup and hold timings

shall remain unchanged.

NOTE 8 See “Temperature Sensor” for information on the recommended frequency of reading MR4.

MR5 Basic Configuration 1 (MA <7:0> =05H) :

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

LPDDR2 Manufacture ID

Read-

only

OP<7:0>

0000 0000B : Reserved

0000 0001B : Samsung

0000 0010B : Qimonda

0000 0011B : Elpida

0000 0100B : Etron

0000 0101B : Nanya

0000 0111B : Mosel

0000 1000B : Winbond

0000 1001B : ESMT

0000 1010B : Reserved

0000 1011B : Spansion

0000 1100B : SST

0000 1101B : ZMOS

0000 1110B : Intel

0001 1100B :

Alliance

1111 1110B : Numonyx

1111 1111B : Micron

All Others : Reserved

MR6_Basic Configuration 2 (MA<7:0> = 06H):

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID1

Read-

only

OP<7:0>

0000 0001B: B-version

NOTE 1 MR6 is Vendor Specific

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

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AS4C64M32MD2-25BCN Datasheet(PDF) 20 Page - Alliance Semiconductor Corporation

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