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MFS2401AVBA0ES Datasheet(PDF) 133 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 133 Page - NXP Semiconductors |
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133 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Address Register Name Bit Group Name Description Hexadecimal Value Settings 0x00 Default 0x00 HVIO1 default state is low (asserted) HVIO1_OUT_ DFLT_OTP Configure the HVIO1 pin default state when HVIO1 is an output 0x01 HVIO1 default state is high (HIZ) 0x00 Default 0x00 HVIO1 is turned high (HIZ) on an active slot HVIO1_SLOT_ POL_OTP Configure the HVIO1 polarity when activated by a slot 0x01 HVIO1 is turned low (asserted) on an active slot 0x00 Default 0x00 Pullup to VSUP HVIO1_PU_SEL_ OTP Select pull up source on HVIO1 when used as an output 0x01 Pullup to VDDIO 0x00 Default 0x00 VBOS to V1 switch is open in LPON mode VBOS2V1_SW_ LP_EN_OTP Control VBOS to V1 switch in LPON mode when V1 = BUCK 0x01 VBOS to V1 switch is closed in LPON mode 0x00 Default 0x00 Triangular modulation is selected by default MOD_CONF_OTP Select default clock modulation configuration (when FS24 boots up) 0x01 Pseudo random modulation is selected by default 0x00 Default 0x00 Modulation is disabled by default MOD_EN_OTP Select the default state of the clock modulation on 20 MHz clock (when FS24 boots up) 0x01 Modulation is enabled by default 0x00 Default 0x00 Slots are not bypassed SLOT_BYP_OTP Bypass unecessary slots 0x01 Bypass unnecessary slots during power-down or wake-up from LPON 0x00 Default 0x00 SPI CRC is enabled, SPI CRC bit are equal to CRC results and are monitored CRC_DIS_OTP Disable SPI CRC check 0x01 SPI CRC is disabled, SPI CRC bit are all set to 0 without monitoring 0x00 Default 0x00 SPI CRC is enabled in Debug mode when CRC_DIS_OTP = 1, stay disabled otherwise CRC_DBG_DIS_ OTP Disable SPI CRC check in Debug mode only 0x01 SPI CRC is disabled in Debug mode 0x00 Default 0x00 SAE J-1850 = (x^8+x^4+x^3+x^2+1) XOR 0x00 0x29 OTP_MAIN_ SYS_CFG CRC_INV_OTP Invert the result of the polynomial calculation for SPI CRC 0x01 CRC-8-AUTOSAR / SAE J-1850 = (x^8+x^4+x^3+x^2+1) XOR 0xFF Table 149. Main OTP bits description...continued [1] These codes are suggested as best fit for the described use cases. In case other values are needed, contact local support. [2] The slope compensation values are given for a typical V1_IN at 13.5 V. 24.3 Fail-safe OTP overview ADDRESS Register Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0x2A OTP_FS_ SYS_CFG ERRMON_ EN_OTP - INIT_CRC_ DIS_OTP FS_LPOFF_ OTP FS_DUR_ CFG_OTP WD_ INF_OTP RSTB8S_ DIS_OTP FIRST_ FAULT_ EN_OTP 0x2B OTP_OVUV_ CFG1 V1MON_UVTH_OTP[3:0] V1MON_OVTH_OTP[3:0] 0x2C OTP_OVUV_ CFG2 V3MON_UVTH_OTP[3:0] V3MON_OVTH_OTP[3:0] 0x2D OTP_OVUV_ CFG3 V0MON_UVTH_OTP[3:0] V0MON_OVTH_OTP[3:0] 0x2E OTP_UV_ DGLT_CFG V0MON_UVDGLT_OTP[1:0] V1MON_UVDGLT_OTP[1:0] - - V3MON_UVDGLT_OTP[1:0] Table 150. Fail-safe OTP overview FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 133 / 151 |
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