MPF5024AMBA0ES datasheet(15/93 Pages) NXP

15 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

15 / 93

By default, the VSWx_STBY[7:0] register is loaded with the data stored in the

OTP_VSWx[7:0] bit.

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_STBY_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNC_MODE = 1, default SWx_STBY_MODE at power up is always set

to PWM (0b01)

• When OTP_SYNC_MODE = 0 and OTP_SYNCOUT_EN = 1, default

SWx_STBY_MODE at power up is always set to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_STBY_MODE at power up shall always set to

PWM (0b01)

• If none of the above conditions are met, the default value of the SWx_STBY_MODE

bits at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_STBY_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_STBY_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_STBY_MODE[1:0] bits are loaded with 0b00 (Off mode).

Upon power up, the standby registers are loaded with the same default OTP values as

the run mode. The MCU is expected to program the desired standby values during boot

up.

If any of the external regulators are disabled in the standby state, the power down

sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.7 WD_Reset

When a hard watchdog reset is present, the state machine increments the

WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register.

If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic

watchdog failure, it powers down the external regulators and proceeds to the fail-safe

transition.

If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD

reset.

A hard WD reset can be generated from either a transition in the WDI pin or a WD event

initiated by the internal watchdog counter as described in Section 15.7.2 "Watchdog reset

behaviors".

13.1.8 Power down state

During power down state, all regulators are disabled as configured in the power down

sequence. The power down sequence is programmable as defined in Section 14.6.2

"Power down sequencing".

Two types of events may lead to the power down sequence:

• Non faulty turn off events: move directly into LP_Off state as soon as power down

sequence is finalized.

• Turn off events due to a PMIC fault: move to the fail-safe transition as soon as the

power down sequence is finalized.

MPF5024AMBA0ES Datasheet(PDF) 15 Page - NXP Semiconductors

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