MPF5024AMBA0ES datasheet(51/93 Pages) NXP

51 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

51 / 93

During normal operation, if the SW1 is disabled via the I2C command, SW2 tracks the

output of SW1 and both regulators are discharged together and pulled down internally.

When SW1 is enabled back via the I2C commands, the SW1 output ramps up to the

corresponding voltage while SW2 is always VSW1/2.

When only SW2 is disabled the PMIC uses the OTP_VTT_PDOWN bit to program

whether the SW2 regulator is disabled with the output in high impedance or discharged

internally.

• When OTP_VTT_PDOWN = 0, the output is disabled in high impedance mode.

• When OTP_VTT_PDOWN = 1, the output is disabled with the internal pull down

enabled.

When SW2 is requested to enable back again, the SW2 ramps up to the voltage set on

the VSW2_RUN or VSW2_STBY registers. Once it reaches the final DVS value, it will

change its reference to start tracking SW1 output again. Note that VSW2_RUN(STBY)

must be set to VSW1_RUN(STBY)/2 or the closest code by the MCU to ensure proper

operation.

When operating in VTT mode, the minimum output voltage configuration for SW1 should

be 800 mV to ensure the SW2 is still within the regulation range at its output.

15.2.2 Multiphase operation

Regulators SW1, SW2, SW3 and SW4 can be configured in dual, triple and quad phase

mode. In this mode, SW1 registers control the output voltage and other configurations.

Likewise, SW1FB pin becomes the main feedback node for the resulting voltage rail,

however the two FB pins should be connected together.

The OTP_SW1CONFIG[1:0] bits are used to select the multiphase configuration for

SW1/SW2/SW3/SW4.

Table 42. OTP_SW1CONFIG register description

OTP_SW1CONFIG[1:0]

Description

SW1 and SW2 operate in single phase mode

SW1/SW2 operate in dual phase mode

SW1/SW2/SW3/SW4 operate in quad phase mode

SW1/SW2/SW3 operate in triple phase mode

The OTP_SW4CONFIG[1:0] bits are used to select the dual phase operation of SW3/

SW4, if the OTP_SW1CONFIG[1:0] bits are set at 0b00 or 0b01.

Table 43. OTP_SW4CONFIG register description

OTP_SW4CONFIG[1:0]

Description

SW3 and SW4 operate in single phase mode

SW3/SW4 operate in dual phase mode

Reserved

MPF5024AMBA0ES Datasheet(PDF) 51 Page - NXP Semiconductors

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