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MPF5024AMBA0ES Datasheet(PDF) 55 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 55 Page - NXP Semiconductors |
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55 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 55 / 93 Table 47. OV threshold configuration register OTP_SWxOV_TH OV threshold level 00 105 % 01 107 % 10 109 % 11 111 % Two functional bits are provided to program the UV debounce time for the voltage regulators. Table 48. UV debounce timer configuration UV_DB[1:0] UV debounce time 00 5 µs 01 15 µs 10 30 µs 11 40 µs The default value of the UV_DB[1:0] upon a full register reset is 0b10. Two functional bits to program the OV debounce time for all the voltage regulators. Table 49. OV debounce timer configuration OV_DB[1:0] OV debounce time 00 30 µs 01 50 µs 10 80 µs 11 125 µs The default value of the OV_DB[1:0] upon a full register reset is 0b00. The VMON_EN bits enable or disable the OV/UV monitor for each one of the external regulators (SWxVMON_EN). • When the VMON_EN bit of a specific regulator is 1, the voltage monitor for that specific regulator is enabled. • When the VMON_EN bit of a specific regulator is 0, the voltage monitor for that specific regulator is disabled. By default, the VMON_EN bits are set to 1 on power up. When the I2C_SECURE_EN = 1, a secure write must be performed to set or clear the VMON_EN bits to enable or disable the voltage monitoring for a specific regulator. On enabling a regulator, the UV/OV monitor is masked until the corresponding regulator reaches the point of regulation. If a voltage monitor is disabled, the UV_S and OV_S indicators from that monitor are reset to 0. Figure 24 shows the PF5024 voltage monitoring architecture. |
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