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MPF5024AMBA0ES Datasheet(PDF) 66 Page - NXP Semiconductors

Part # MPF5024AMBA0ES
Description  Power management integrated circuit (PMIC) for high performance applications
PDF  93 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 66 Page - NXP Semiconductors

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NXP Semiconductors
PF5024
Power management integrated circuit (PMIC) for high performance applications
PF5024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
66 / 93
aaa-028072
WD refresh OK
WD_EXPIRE_CNT
WD refresh NOK
WD refresh
NOK
WD refresh
NOK
WD refresh
NOK
WD refresh
NOK
WD refresh NOK
WD refresh
NOK
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh
NOK
WD EVENT
WD refresh OK
WD refresh OK
WD refresh OK
WD refresh OK
n =
WD_MAX
_EXPIRE
5
4
3
2
1
0
0
WD_TIMER
Expired
WD refresh NOK
0
WD_TIMER
Expired
WD_TIMER
50 % Window
WD_TIMER
100 % Window
Figure 28. Watchdog timer operation
The watchdog function can be enabled or disabled by writing the WD_EN bit in the I2C
register map. When the I2C_SECURE_EN = 1, a secure write must be performed to
change the WD_EN bit.
• When WD_EN = 0 the internal watchdog timer operation is disabled.
• When WD_EN = 1 the internal watchdog timer operation is enabled.
The OTP_WD_EN bit is used to select the default status of the watchdog counter upon
power up.
The watchdog function can be programmed to be enabled or disabled during the
Standby state by writing the WD_STBY_EN bit in the I2C register map. When the
I2C_SECURE_EN = 1, a secure write must be performed to modify the WD_STBY_EN
bit.
• When WD_STBY_EN = 0 the internal watchdog timer operation during standby is
disabled.
• When WD_STBY_EN = 1 the internal watchdog timer operation during standby is
enabled.
The OTP_WD_STBY_EN bit selects whether the watchdog is active in Standby mode by
default or not.



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