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MPF5024AMBA0ES Datasheet(PDF) 69 Page - NXP Semiconductors

Part # MPF5024AMBA0ES
Description  Power management integrated circuit (PMIC) for high performance applications
PDF  93 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 69 Page - NXP Semiconductors

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NXP Semiconductors
PF5024
Power management integrated circuit (PMIC) for high performance applications
PF5024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
69 / 93
aaa-030057
System ON
30 µs
Power Down
Sequence
Power Up
Sequence
Power Down
Delay
Regulator
Outputs
WD Event
RESETBMCU
WD OK
Default OTP
WD OK
WD Event
Hard WD Reset Behavior
WD
Reset
Figure 30. Hard WD reset behavior
After a WD reset, the PMIC may enter the Standby state depending on the status of
STANDBY pin.
Every time a WD event occurs, the WD_EVENT_CNT[3:0] nibble is incremented.
To prevent continuous failures, if the WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0]
the state machine will proceed to the fail-safe transition. The MCU is expected to
clear the WD_EVENT_CNT[3:0] when it is able to do so in order to keep proper
operation. Upon power up, the WD_MAX_CNT[3:0] is loaded with the values on the
OTP_WD_MAX_CNT[3:0] bits.
Every time the device passes through the off states, the WD_EVENT_CNT[3:0] is reset
to 0x00, to ensure the counter has a fresh start after a device power down.



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