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MPF5024AMBA0ES Datasheet(PDF) 77 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 77 Page - NXP Semiconductors |
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77 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 77 / 93 The PF5024 can operate normally using the TBB configuration, as long as VIN does not go below the UVDET threshold. If VIN is lost (VIN < UVDET) the mirror register will be reset and TBB configuration must be performed again. aaa-028076 LP_Off QPU_Off Power On Event Self-Test l2C POWER UP POWER OFF SYSTEM ON Mirror Registers FUSE LOAD Vin > UVDET OTP Config Hardwire Config I2C Register Map TBB Default Configuration l2C Register Map TBB Power up lf TBBEN = V1P5D (Limited Functionality) lf TBBEN = GND (Full Functionality) Configuration Modified TBB Configuration TBBEN = V1P5D VDDOTP = 0v I2C Register Map Mirror Registers Mirror Registers Figure 32. TBB operation diagram 17.2 OTP fuse programming A permanent OTP configuration is possible by burning the OTP fuses. OTP fuse burning is performed in the TBBEN mode during the QPU_Off state. Contact your NXP representative for detailed information on OTP fuse programming. |
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