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MPF5024AMBA0ES Datasheet(PDF) 75 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 75 Page - NXP Semiconductors |
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75 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 75 / 93 AD DR Register name R/W Default BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 5B SW3 RUN VOLT R/W FFFF_FFFF VSW3_RUN[7:0] 5C SW3 STBY VOLT R/W FFFF_FFFF VSW3_STBY[7:0] 5D 5E 5F SW4 CONFIG1 R/W FFF1_11FF SW4_UV_ BYPASS SW4_OV_ BYPASS SW4_ILIM_ BYPASS SW4_UV_STATE SW4_OV_STATE SW4_ILIM_ STATE SW4_ WDBYPASS SW4_PG_EN 60 SW4 CONFIG2 R/W 10FF_FFFF SW4_FLT_REN — — SW4ILIM[1:0] SW4PHASE[2:0] 61 SW4 PWRUP R/W FFFF_FFFF SW4_SEQ[7:0] 62 SW4 MODE R/W 00FF_FFFF — — SW4_PDGRP[1:0] SW4_STBY_MODE[1:0] SW4_RUN_MODE[1:0] 63 SW4 RUN VOLT R/W FFFF_FFFF VSW4_RUN[7:0] 64 SW4 STBY VOLT R/W FFFF_FFFF VSW4_STBY[7:0] 65 66 67 SWND1 CONFIG1 R/W FFF1_11FF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 68 SWND1 CONFIG2 R/W 100F_FFFF Reserved — — Reserved Reserved 69 SWND1 PWRUP R/W FFFF_FFFF Reserved 6A SWND1 MODE1 R/W 00FF_FFFF — — Reserved Reserved Reserved 6B SWND1 RUN VOLT R/W 000F_FFFF — — — Reserved 6C 6D 6E LDO1 CONFIG1 R/W FFF1_11FF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 6F LDO1 CONFIG2 R/W 1FF0_00FF Reserved Reserved — — — Reserved Reserved 70 LDO1 PWRUP R/W FFFF_FFFF Reserved 71 LDO1 RUN VOLT R/W 0000_FFFF — — — — Reserved 72 LDO1 STBY VOLT R/W 0000_FFFF — — — — Reserved 73 74 75 VSNVS CONFIG1 R/W 0000_00FF — — — — — — Reserved 76 77 PAGE SELECT R/TW 0000_0000 — — — — — PAGE[2:0] 17 OTP/TBB and hardwire default configurations The PF5024 supports OTP fuse bank configuration and a predefined hardwire configuration to select the default power up configuration via the VDDOTP pin. The default power up configuration is loaded into the functional I2C registers based on the voltage on VDDOTP pin on register loading. • If VDDOTP = GND, the device loads the configuration from the OTP mirror registers. • If VDDOTP = V1P5D, the device loads the configuration from the default hardwire configuration. When OTP configuration is selected, the register loading occurs in two stages: • In the first stage, the fuses are loaded in the OTP mirror registers each time VIN crosses the UVDET threshold in the rising edge. • At the second stage, the data from the mirror registers are loaded into the functional I2C registers for device operation. When VDDOTP = GND, the mirror registers hold the default configuration to be used on a power-on event. The mirror registers can be modified during the TBB mode in order to |
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