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MPF5024AMBA0ES Datasheet(PDF) 73 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 73 Page - NXP Semiconductors |
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73 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 73 / 93 16.2 PF5024 functional register map RESET signals R/W types Default values UVDET Reset when VIN crosses UVDET threshold R Read only 1 bit set on reset OFF_OTP Bits are loaded with OTP values (mirror register) R/W Read and Write 0 bit cleared on reset OFF_TOGGLE Reset when device goes to OFF mode RW1C Read, Write a 1 to clear x unknown state SC Self-clear after write R/SW Read/Secure Write F loaded from OTP fuse R/TW Read/Write on TBB only T Hard coded AD DR Register name R/W Default BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 00 DEVICE ID R 0101_TTTT DEVICE_FAM[3:0] DEVICE_ID[3:0] 01 REV ID R TTTT_TTTT FULL_LAYER_REV[3:0] METAL_LAYER_REV[3:0] 02 EMREV R FFFF_TTTT PROG_ID[11:8] — EMREV[2:0] 03 PROG ID R FFFF_FFFF PROG_ID[7:0] 04 INT STATUS1 RW1C 0000_0000 SDWN_I FREQ_RDY_I CRC_I PWRUP_I PWRDN_I — PGOOD_I VIN_OVLO_I 05 INT MASK1 R/W 1111_1011 SDWN_M FREQ_RDY_M CRC_M PWRUP_M PWRDN_M — PGOOD_M VIN_OVLO_M 06 INT SENSE1 R 0000_00xx — — — — — — PGOOD_S VIN_OVLO_S 07 INT STATUS2 RW1C 0000_0000 WDI_I FSYNC_FLT_I THERM_155_I THERM_140_I THERM_125_I THERM_110_I THERM_95_I THERM_80_I 08 INT MASK2 R/W 1111_1111 WDI_M FSYNC_FLT_M THERM_155_M THERM_140_M THERM_125_M THERM_110_M THERM_95_M THERM_80_M 09 INT SENSE2 R xxxx_xxxx WDI_S FSYNC_FLT_S THERM_155_S THERM_140_S THERM_125_S THERM_110_S THERM_95_S THERM_80_S 0A SW MODE INT RW1C 0000_0000 — Reserved — — SW4_MODE_I SW3_MODE_I SW2_MODE_I SW1_MODE_I 0B SW MODE MASK R/W 0100_1111 — Reserved — — SW4_MODE_M SW3_MODE_M SW2_MODE_M SW1_MODE_M 0C SW ILIM INT RW1C 0000_0000 — Reserved — — SW4_ILIM_I SW3_ILIM_I SW2_ILIM_I SW1_ILIM_I 0D SW ILIM MASK R/W 0100_1111 — Reserved — — SW4_ILIM_M SW3_ILIM_M SW2_ILIM_M SW1_ILIM_M 0E SW ILIM SENSE R 0x00_00xx — Reserved — — SW4_ILIM_S SW3_ILIM_S SW2_ILIM_S SW1_ILIM_S 0F LDO ILIM INT RW1C 0000_0000 — — — — — — — Reserved 10 LDO ILIM MASK R/W 0000_0001 — — — — — — — Reserved 11 LDO ILIM SENSE R 0000_000x — — — — — — — Reserved 12 SW UV INT RW1C 0000_0000 — Reserved — — SW4_UV_I SW3_UV_I SW2_UV_I SW1_UV_I 13 SW UV MASK R/W 0100_1111 — Reserved — — SW4_UV_M SW3_UV_M SW2_UV_M SW1_UV_M 14 SW UV SENSE R 0x00_00xx — Reserved — — SW4_UV_S SW3_UV_S SW2_UV_S SW1_UV_S 15 SW OV INT RW1C 0000_0000 — Reserved — — SW4_OV_I SW3_OV_I SW2_OV_I SW1_OV_I 16 SW OV MASK R/W 0100_1111 — Reserved — — SW4_OV_M SW3_OV_M SW2_OV_M SW1_OV_M 17 SW OV SENSE R 0x00_00xx — Reserved — — SW4_OV_S SW3_OV_S SW2_OV_S SW1_OV_S 18 LDO UV INT RW1C 0000_0000 — — — — — — — Reserved 19 LDO UV MASK R/W 0000_0001 — — — — — — — Reserved 1A LDO UV SENSE R 0000_000x — — — — — — — Reserved 1B LDO OV INT RW1C 0000_0000 — — — — — — — Reserved 1C LDO OV MASK R/W 0000_0001 — — — — — — — Reserved 1D LDO OV SENSE R 0000_000x — — — — — — — Reserved 1E PWRON INT RW1C 0000_0000 BGMON_I PWRON_8S_I PWRON_4S_I PRON_3S_I PWRON_2S_I PWRON_1S_I PWRON_REL_I PWRON_PUSH_I 1F PWRON MASK R/W 1111_1111 BGMON_M PWRON_8S_M PWRON_4S_M PRON_3S_M PWRON_2S_M PWRON_1S_M PWRON_REL_M PWRON_PUSH_ M 20 PWRON SENSE R x000_000x BGMON_S — — — — — — PWRON_S 21 EN SENSE R 0000_xxxx — — — — EN4_S EN3_S EN2_S EN1_S 22 SYS INT R 0000_0000 EWARN_I PWRON_I OV_I UV_I ILIM_I MODE_I STATUS2_I STATUS1_I 23 HARDFAULT FLAGS RW1C 0000_0000 — — — — PU_FAIL WD_FAIL REG_FAIL TSD_FAIL 24 25 ABIST PGOOD MON R/SW 0000_0000 — — — — — — — AB_PGOOD_ MON 26 ABIST OV1 R/SW 0000_0000 — Reserved — — AB_SW4_OV AB_SW3_OV AB_SW2_OV AB_SW1_OV 27 ABIST OV2 R/SW 0000_0000 — — — — — — — Reserved |
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