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MPF5024AMBA0ES Datasheet(PDF) 22 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 22 / 93 When the _SEQ[7:0] bits of all regulators and PGOOD used as a GPIO are set to 0x00 (OFF) and a power on event is present, the device moves to the run state in slave mode. In this mode, the device is enabled without any voltage regulator or GPO enabled. If the RESETBMCU is not programed in a power up sequence slot, it is released when the device enters the run state. The slave mode is a special case of the power up sequence to address the scenario where the PF5024 is working as a slave PMIC, and supplies are meant to be enabled by the MCU during the system operation. In this scenario, if RESETBMCU is used, it is connected to the master RESETBMCU pin. Figure 8 provides an example of the power up/down sequence coming from the Off modes. aaa-030047 System On End of PWRUP End of PWRDN Power down Seq. Run to Off Power up Seq. Off to Run INTB SW2 SW3 SW4 SW1 RESETBMCU Start of PWRDN Figure 8. Power up/down sequence between Off and system On state When transitioning from Standby mode to Run mode, the power up sequencer is activated only if any of the external regulators is re-enabled during this transition. If none of the regulators toggle from Off to On and only voltage changes are being performed when entering or exiting Standby mode, the changes for the voltage regulators are made simultaneously rather than going through the power up sequencer. Figure 9 shows an example of the power up/down sequence when transitioning between Run and Standby modes. |
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