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MPF5024AMBA0ES Datasheet(PDF) 67 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 67 Page - NXP Semiconductors |
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67 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 67 / 93 15.7.2 Watchdog reset behaviors When a watchdog event is started, a watchdog (WD) reset is performed. There are two types of watchdog reset: • Soft WD reset • Hard WD reset A soft WD reset is used as a safe way for the MCU to force the PMIC to return to a known default configuration without forcing a POR reset on the MCU. During a soft WD reset, the RESETBMCU remains de-asserted all the time. Upon a soft WD reset, a partial OTP register reload is performed on the registers as shown in Table 57. Table 57. Soft WD register reset Bit name Register Bits Configuration registers STANDBYINV CTRL2 2 RUN_PG_GPO CTRL2 1 STBY_PG_GPO CRTL2 0 RESETBMCU_SEQ[7:0] RESETBMCU PWRUP 7:0 PGOOD_SEQ[7:0] PGOOD PWRUP 7:0 WD_EN CTRL1 3 WD_DURATION[3:0] WD CONFIG 3:0 WD_STBY_EN CTRL1 2 WDI_STBY_ACTIVE CTRL1 1 SW registers SWx_WDBYPASS SWx CONFIG1 1 SWx_PG_EN SWx CONFIG1 0 SWxDVS_RAMP SWx CONFIG2 5 SWxILIM[1:0] SWx CONFIG2 4:3 SWxPHASE[2:0] SWx CONFIG2 2:0 SWx_SEQ[7:0] SWx PWRUP 7:0 SWx_PDGRP[1:0] SWx MODE 5:4 SWx_STBY_MODE [1:0] SWx MODE 3:2 SWx RUN_MODE [1:0] SWx MODE 1:0 VSWx_RUN [7:0] SWx RUN VOLT 7:0 VSWx_STBY [7:0] SWx STBY VOLT 7:0 SW2_VTTEN SW2_CONFIG2 6 A soft WD reset may require all or some regulators to be reset to their default OTP configuration. In the event a regulator is required to keep its current configuration during a soft WD reset, a watchdog bypass bit is provided for each regulator (SWx_WDBYPASS). • When the WDBYPASS = 0, the watchdog bypass is disabled and the output of the corresponding regulator is returned to its default OTP value during the soft WD reset. |
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