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MPF5024AMBA0ES Datasheet(PDF) 30 Page - NXP Semiconductors

Part # MPF5024AMBA0ES
Description  Power management integrated circuit (PMIC) for high performance applications
PDF  93 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 30 Page - NXP Semiconductors

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NXP Semiconductors
PF5024
Power management integrated circuit (PMIC) for high performance applications
PF5024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
30 / 93
Table 24. Fault timer register configuration
OTP bits
OTP_TIMER_FAULT [3:0]
Functional bits
TIMER_FAULT [3:0]
Timer value
(ms)
0000
0000
1
0001
0001
2
0010
0010
4
0011
0011
8
0100
0100
16
0101
0101
32
0110
0110
64
0111
0111
128
1000
1000
256
1001
1001
512
1010
1010
1024
1011
1011
2056
1100
1100
Reserved
1101
1101
Reserved
1110
1110
Reserved
1111
1111
Disabled
Each voltage regulator has a dedicated I2C bit that is used to bypass the fault detection
mechanism for each specific fault.
SWx_ILIM_BYPASS
• 0 = ILIM protection enabled
• 1 = ILIM fault bypassed
SWx_OV_BYPASS
• 0 = OV protection enabled
• 1 = OV fault bypassed
SWx_UV_BYPASS
• 0 = UV protection enabled
• 1 = UV fault bypassed
Table 25. Fault bypass bits
Regulator
Bit to bypass a current
limit
Bit to bypass an
undervoltage
Bit to bypass an
overvoltage
SWx
SWx_ILIM_BYPASS
SWx_UV_BYPASS
SWx_OV_BYPASS
The default value of the OV_BYPASS, UV_BYPASS and ILIM_BYPASS bits upon power
up can be configured by their corresponding OTP bits.
Bypassing the fault detection prevents the specific fault from starting any of the protective
mechanism:
• Increment the counter
• Start the fault timer
• Disable the regulator if the corresponding _STATE bit is 0



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