MPF5024AMBA0ES datasheet(64/93 Pages) NXP

64 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

64 / 93

Bit(s)

Description

THERM_155_I, THERM_155_S, THERM_155_M

Interrupt, sense and mask bits for 155 ºC threshold

TMP_MON_EN

Disables temperature monitoring circuits when

cleared

TMP_MON_AON

When set, the temperature monitoring circuit is always

ON.

When cleared, the temperature monitor operates in

Sampling mode.

15.6 Analog multiplexer

An analog multiplexer (AMUX) is provided to allow access to internal temperature

monitor. The selected voltage is buffered and made available on the PGOOD1 output

pin.

When the AMUX_EN bit is 0, the AMUX block is disabled and the PGOOD1 block is

enabled.

When the AMUX_EN bit is 1, the AMUX block is enabled and the PGOOD1 block is

disabled. The system can select the channel to be read using the AMUX_SEL bits. The

AMUX output is selected by the AMUX_SEL[4:0] bits.

Table 55. AMUX channel selection

AMUX_EN

AMUX_SEL[4:0]

AMUX selection

XXXXX

PGOOD mode

00000

Disabled - high impedance

00001 to 00110

Reserved

00111

TEMP_IC

01000 to 11111

Reserved

When the AMUX_EN = 1, and the AMUX_SEL = 00000, the AMUX output is set to a

high impedance mode to allow an external signal to drive the AMUX node. The AMUX is

enabled and accessible during the system On states.

15.7 Watchdog event management

A watchdog event may be started in two ways:

• The WDI pin toggles low due to a watchdog failure on the MCU

• The internal watchdog expiration counter reaches the maximum value the WD timer is

allowed to expire

A watchdog event initiated by the WDI pin may perform a hard WD reset or a soft WD

reset as defined by the WDI_MODE bit. A watchdog event initiated by the internal

watchdog always performs a hard WD reset.

15.7.1 Internal watchdog timer

The internal WD timer counts up and it expires when it reaches the value in the

WD_DURATION[3:0] register. When the WD timer starts counting, the WD_CLEAR

flag is set to 1. Clearing the WD_CLEAR flag within the valid window is interpreted as a

successful watchdog refresh and the WD timer gets reset. The MCU must write a 1 to

clear the WD_CLEAR flag.

MPF5024AMBA0ES Datasheet(PDF) 64 Page - NXP Semiconductors

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