MPF5024AMBA0ES datasheet(29/93 Pages) NXP

29 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

29 / 93

RegX_STATE = 0 && FLT_REN = 1

ILIM fault

RegX_STATE = 0 && FLT_REN = 1

OV/UV fault

REGx

I_REGx

REGx_EN

REGx

REGx_EN

PGOOD

REGx_PG

ILIM

1 ms

1.5 ms

500 µs

300 µs

500 µs

300 µs

1 ms

1.5 ms

aaa-028058

Figure 13. Regulator turned off upon with RegX_STATE = 0 and FLT_REN = 1

When any of the regulators is controlled by hardware using the ENx pins and

programmed to turn off upon an OV, UV or ILIM fault, the _FLT_REN bit still controls

whether the regulator returns to its previous state or not regardless the state of the ENx

pin.

To avoid fault cycling, a global fault counter is provided. Each time any of the

external regulators encounter a fault event, the PF5024 compares the value of the

FAULT_CNT[3:0] against the FAULT_MAX_CNT, and if it not equal, it increments the

FAULT_CNT[3:0] and proceeds with the fault protection mechanism.

The processor is expected to read the counter value and reset it when the faults have

been cleared and the device returns to a normal operation. If the processor does not

reset the fault counter and it equals the FAULT_MAX_CNT[3:0] value, the state machine

initiates a power down sequence.

The default value of the FAULT_MAX_CNT[3:0] is loaded from the

OTP_FAULT_MAX_CNT[3:0] bits during the power up sequence.

When the FAULT_MAX_CNT[3:0] is set to 0x00, the system disables the turn-off events

due to a fault counter maxing out.

When a regulator experiences a fault event, a fault timer is started. While this timer

is in progress, the expectation is that the processor takes actions to clear the fault.

For example, it could reduce its load in the event of a current limit fault, or turn off the

regulator in the event of an overvoltage fault.

If the fault clears before the timer expires, the state machine resumes the normal

operation, and the fault timer gets reset. If the fault does not clear before the timer

expires, a power down sequence is initiated to turn off the voltage regulators.

The default value of the fault timer is set by the OTP_TIMER_FAULT[3:0], however the

duration of the fault timer can be changed during the system On state by modifying the

TIMER_FAULT[3:0] bits in the I2C registers.

MPF5024AMBA0ES Datasheet(PDF) 29 Page - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 29 Page - NXP Semiconductors

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