MPF5024AMBA0ES datasheet(68/93 Pages) NXP

68 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

68 / 93

• When the WDBYPASS = 1, the watchdog bypass is enabled and the output of the

corresponding regulator is not affected by the soft WD reset, keeping its current

configuration.

During a soft WD reset, only regulators that are activated in the power up sequence go

back to their default voltage configuration if their corresponding WDBYPASS = 0.

Switching regulators returning to their default voltages configuration, will gradually reach

the new output voltage using its DVS configuration. Regulators with WDBYPASS = 0 and

which are not activated during the power up sequence will turn off immediately.

After all output voltages have transitioned to their corresponding default values, the

device waits for at least 30 μs before returning to the Run state and announces it has

finalized the soft WD reset by asserting the INTB pin, provided the WDI_I interrupt is not

masked.

aaa-030056

System ON

30 µs

WDI_I Delay

Soft WD

reset

Default OTP Configuration

INTB

RESETBMCU

In Power up

Sequence

Not in Power

up Sequence

Regulator with

WDBYPASS = 1

WDBYPASS = 0

WDI Event

Configuration Maintained

WDI OK

WDI Event

Soft WD Reset Behavior

Figure 29. Soft WD reset behavior

A hard WD reset is used to force a system power-on reset when the MCU has become

unresponsive. In this scenario, a full OTP register reset is performed.

During a hard WD reset, the device turns off all regulators and asserts RESETBMCU

as indicated by the power down sequence. If PGOOD is programmed as a GPO and

configured as part of the power up sequence, it will also be disabled accordingly.

After all regulator's outputs have gone through the power down sequence and the power

down delay is finished , the device waits for 30 µs before reloading the default OTP

configuration and get ready to start a power up sequence if the XFAILB pin is not held

low externally.

MPF5024AMBA0ES Datasheet(PDF) 68 Page - NXP Semiconductors

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