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MPF5024AMBA0ES Datasheet(PDF) 74 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 74 Page - NXP Semiconductors |
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74 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 74 / 93 AD DR Register name R/W Default BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 28 ABIST UV1 R/SW 0000_0000 — Reserved — — AB_SW4_UV AB_SW3_UV AB_SW2_UV AB_SW1_UV 29 ABIST UV2 R/SW 0000_0000 — — — — — — — Reserved 2A TEST FLAGS R/TW 0000_0000 — — — — — STEST_NOK TRIM_NOK OTP_NOK 2B ABIST RUN R/SW 0000_0000 — — — — — — — AB_RUN 2C 2D RANDOM GEN R xxxx_xxxx RANDOM_GEN[7:0] 2E RANDOM CHK R/W 0000_0000 RANDOM_CHK[7:0] 2F VMONEN1 R/SW 0100_1111 — Reserved — — SW4VMON_EN SW3VMON_EN SW2VMON_EN SW1VMON_EN 30 VMONEN2 R/SW 0000_0001 — — — — — — — Reserved 31 CTRL1 R/SW FFF1_FFFF VIN_OVLO_EN VIN_OVLO_ SDWN WDI_MODE TMP_MON_EN WD_EN WD_STBY_EN WDI_STBY_ ACTIVE I2C_SECURE_EN 32 CTRL2 R/W FF01_0FFF VIN_OVLO_DBNC[1:0] — TMP_MON_AON LPM_OFF STANDBYINV RUN_PG_GPO STBY_PG_GPO 33 CTRL3 R/W 0010_0000 OV_DB[1:0] UV_DB[1:0] — — PMIC_OFF INTB_TEST 34 PWRUP CTRL R/W 0FFF_FFFF — PWRDWN_ MODE PGOOD_PDGRP[1:0] RESETBMCU_PDGRP[1:0] SEQ_TBASE[1:0] 35 36 RESETBMCU PWRUP R/W FFFF_FFFF RESETBMCU_SEQ[7:0] 37 PGOOD PWRUP R/W FFFF_FFFF PGOOD_SEQ[7:0] 38 PWRDN DLY1 R/W FFFF_FFFF GRP4_DLY[1:0] GRP3_DLY[1:0] GRP2_DLY[1:0] GRP1_DLY[1:0] 39 PWRDN DLY2 R/W 0000_00FF — — — — — — RESETBMCU_DLY[1:0] 3A FREQ CTRL R/W FFFF_FFFF SYNCOUT_EN FSYNC_RANGE FSS_EN FSS_RANGE CLK_FREQ[3:0] 3B 3C PWRON R/W 000F_FFFF — — — PWRON_DBNC[1:0] PWRON_RST_ EN TRESET[1:0] 3D WD CONFIG R/W 0000_FFFF — — — — WD_DURATION[3:0] 3E WD CLEAR R/W1C 0000_0000 — — — — — — — WD_CLEAR 3F WD EXPIRE R/W 0FFF_0000 — WD_MAX_EXPIRE[2:0] — WD_EXPIRE_CNT[2:0] 40 WD COUNTER R/W FFFF_0000 WD_MAX_CNT[3:0] WD_EVENT_CNT[3:0] 41 FAULT COUNTER R/W FFFF_0000 FAULT_MAX_CNT[3:0] FAULT_CNT[3:0] 42 FSAFE COUNTER R/W 0000_0000 — — — — FS_CNT [3:0] 43 FAULT TIMERS R/W 0000_FFFF — — — — TIMER_FAULT[3:0] 44 AMUX R/W 0000_0000 — — AMUX_EN AMUX_SEL[4:0] 45 46 SW RAMP R/W FFFF_FFFF SW4DVS_RAMP[1:0] SW3DVS_RAMP[1:0] SW2DVS_RAMP[1:0] SW1DVS_RAMP[1:0] 47 SW1 CONFIG1 R/W FFF1_11FF SW1_UV_ BYPASS SW1_OV_ BYPASS SW1_ILIM_ BYPASS SW1_UV_STATE SW1_OV_STATE SW1_ILIM_ STATE SW1_ WDBYPASS SW1_PG_EN 48 SW1 CONFIG2 R/W 10FF_FFFF SW1_FLT_REN — — SW1ILIM[1:0] SW1PHASE[2:0] 49 SW1 PWRUP R/W FFFF_FFFF SW1_SEQ[7:0] 4A SW1 MODE R/W 00FF_FFFF — — SW1_PDGRP[1:0] SW1_STBY_MODE[1:0] SW1_RUN_MODE[1:0] 4B SW1 RUN VOLT R/W FFFF_FFFF VSW1_RUN[7:0] 4C SW1 STBY VOLT R/W FFFF_FFFF VSW1_STBY[7:0] 4D 4E 4F SW2 CONFIG1 R/W FFF1_11FF SW2_UV_ BYPASS SW2_OV_ BYPASS SW2_ILIM_ BYPASS SW2_UV_STATE SW2_OV_STATE SW2_ILIM_ STATE SW2_ WDBYPASS SW2_PG_EN 50 SW2 CONFIG2 R/W 1FFF_FFFF SW2_FLT_REN SW2_VTTEN — SW2ILIM[1:0] SW2PHASE[2:0] 51 SW2 PWRUP R/W FFFF_FFFF SW2_SEQ[7:0] 52 SW2 MODE1 R/W 00FF_FFFF — — SW2_PDGRP[1:0] SW2_STBY_MODE[1:0] SW2_RUN_MODE[1:0] 53 SW2 RUN VOLT R/W FFFF_FFFF VSW2_RUN[7:0] 54 SW2 STBY VOLT R/W FFFF_FFFF VSW2_STBY[7:0] 55 56 57 SW3 CONFIG1 R/W FFF1_11FF SW3_UV_ BYPASS SW3_OV_ BYPASS SW3_ILIM_ BYPASS SW3_UV_STATE SW3_OV_STATE SW3_ILIM_ STATE SW3_ WDBYPASS SW3_PG_EN 58 SW3 CONFIG2 R/W 10FF_FFFF SW3_FLT_REN — — SW3ILIM[1:0] SW3PHASE[2:0] 59 SW3 PWRUP R/W FFFF_FFFF SW3_SEQ[7:0] 5A SW3 MODE R/W 00FF_FFFF — — SW3_PDGRP[1:0] SW3_STBY_MODE[1:0] SW3_RUN_MODE[1:0] |
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