MPF5024AMBA0ES datasheet(48/93 Pages) NXP

48 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

48 / 93

aaa-028064

I2C

INTERFACE

2 to 3 MHz

clock

duty cycle

generator

slope

compensation

DAC

SWxFB

TYPE II INTERNAL

COMPENSATION

VSWx

SWxLX

SWxIN

SWx

VIN

CINSWx

COSWx

LSWx

SWxPHASE

SWxILIM

SWxMODE

CONTROLLER

DRIVER

ISENSE

Figure 23. Buck regulator block diagram

The OTP_SWxDVS_RAMP bit sets the default step/time ratio for the power up ramp

during the power up/down sequence as well as the DVS slope during the system On.

The power down ramp and DVS rate during the system On of SW1 to SW4 can be

modified during the system On state by changing the SWxDVS_RAMP bit on the I2C

The DVS ramp rate between 0.4 V and 1.5 V output setting is based on the internal clock

configuration as shown in Table 36.

The ramp rate at 1.8 V output setting is 20 % faster than the values in Table 36.

Table 36. SWx ramp rates

All ramp rates are typical values.

Clock frequency tolerance = ± 6 %.

DVS_RAMP = 00

DVS_RAMP = 01

DVS_RAMP = 10

DVS_RAMP = 11

CLK_

FREQ[3:0]

Switching

regulators

frequency

(MHz)

Ramp up rate

(mV/µs)

Ramp down

rate (mV/µs)

Ramp up rate

(mV/µs)

Ramp down

rate (mV/µs)

Ramp up rate

(mV/µs)

Ramp down

rate (mV/µs)

Ramp up rate

(mV/µs)

Ramp down

rate (mV/µs)

0000

2.500

7.81

5.21

15.63

10.42

3.91

2.60

1.95

1.30

0001

2.625

8.20

5.47

16.41

10.94

4.10

2.73

2.05

1.37

0010

2.750

8.59

5.73

17.19

11.46

4.30

2.86

2.15

1.43

0011

2.875

8.98

5.99

17.97

11.98

4.49

2.99

2.25

1.50

0100

3.000

9.38

6.25

18.75

12.50

4.69

3.13

2.34

1.56

1001

2.000

6.25

4.17

12.50

8.33

3.13

2.08

1.56

1.04

1010

2.125

6.64

4.43

13.28

8.85

3.32

2.21

1.66

1.11

1011

2.250

7.03

4.69

14.06

9.38

3.52

2.34

1.76

1.17

1100

2.375

7.42

4.95

14.84

9.90

3.71

2.47

1.86

1.24

Buck regulators SWx use 8 bits to set the output voltage.

• The VSWx_RUN[7:0] set the output voltage during Run mode.

• The VSWx_STBY[7:0] set the output voltage during Standby mode.

MPF5024AMBA0ES Datasheet(PDF) 48 Page - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 48 Page - NXP Semiconductors

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