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MPF5024AMBA0ES Datasheet(PDF) 4 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 93 page ![]() NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 4 / 93 7 Pinning information 7.1 Pinning aaa-030042 SCL 30 SDA 29 VDDOTP 28 SYNC 27 PGOOD 26 INTB 25 V1P5D 24 V1P5A 23 STANDBY 22 XFAILB 21 SW2FB 1 SW1IN 2 SW1LX 3 SW2LX 4 SW2IN 5 SW3IN 6 SW3LX EPAD 7 SW4LX 8 SW4IN 9 SW4FB 10 Figure 3. Pin configuration for 40-pin QFN 7.2 Pin description Table 2. Pin description QFN pin number Pin name Pin description Min Max Units 1 SW2FB SW2 feedback input −0.3 6.0 V 2 SW1IN SW1 input supply −0.3 6.0 V 3 SW1LX SW1 switching node −0.3 6.0 V 4 SW2LX SW2 switching node −0.3 6.0 V 5 SW2IN SW2 input supply −0.3 6.0 V 6 SW3IN SW3 input supply −0.3 6.0 V 7 SW3LX SW3 switching node −0.3 6.0 V 8 SW4LX SW4 switching node −0.3 6.0 V 9 SW4IN SW4 input supply −0.3 6.0 V 10 SW4FB SW4 feedback input −0.3 6.0 V 11 SW3FB SW3 feedback input −0.3 6.0 V 12 EN4 SW4 enable input −0.3 6.0 V 13 EN3 SW3 enable input −0.3 6.0 V 14 NC5 not connected −0.3 6.0 V |
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