MPF5024AMBA0ES datasheet(46/93 Pages) NXP

46 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

46 / 93

aaa-028696

MSB Data

I2C CRS Polynominal

Seed: 1 1 1 1 1 1 1 1

Figure 22. 8 bit SAE J1850 CRC polynomial

14.9.11.2 I2C secure write

A secure write mechanism is implemented for specific registers critical to the functional

safety of the device.

• When OTP_I2C_ SECURE_EN = 0, the secure write is disabled.

• When OTP_I2C_ SECURE_EN = 1, the secure write is enabled.

When the secure write is enabled, a specific sequence must be followed in order to grant

writing access on the corresponding secure register.

Secure write sequence is as follows:

• MCU sends command to modify the secure registers

• PMIC generates a random code in the RANDOM_GEN register

• MCU reads the random code from the RANDOM_GEN register and writes it back on

the RANDOM_CHK register

The PMIC compares the RANDOM_CHK against the RANDOM_GEN register:

• If RANDOM_CHK [7:0] = RANDOM_GEN[7:0], the device applies the configuration

on the corresponding secure register, and self-clears both the RANDOM_GEN and

RANDOM_CHK registers.

• If RANDOM_CHK[7:0] different from RANDOM_GEN[7:0], the device ignores the

configuration command and self-clears both the RANDOM_GEN and RANDOM_CHK

registers.

In the event the MCU sends any other command instead of providing a value for the

RANDOM_CHK register, the state machine cancels the ongoing secure write transaction

and performs the new I2C command.

In the event the MCU does not provide a value for the RANDOM_CHK register, the I2C

transaction will time out 10 ms after the RANDOM_GEN code is generated, and device is

ready for a new transaction.

Table 34. Secure bits

Bit

Description

ABIST OV1

AB_SWx_OV

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST UV1

AB_SWx_UV

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST RUN

AB_RUN

Writing a 1 starts an ABIST on demand

CTRL1

TMP_MON_EN

Writing a 0 disables the thermal monitor, preventing

the thermal interrupts and thermal shutdown event

from being detected

CTRL1

VIN_OVLO_EN

Writing a 0 disables the VIN overvoltage lockout

monitor completely

MPF5024AMBA0ES Datasheet(PDF) 46 Page - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 46 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL