MPF5024AMBA0ES datasheet(50/93 Pages) NXP

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NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

50 / 93

Table 39. SWx current limit selection

SWxILIM[1:0]

Typical current limit

2.1 A

2.6 A

3.0 A

4.5 A

During single phase operation, all buck regulators use 3 bits (SWxPHASE[2:0]) to control

the phase shift of the switching frequency. Upon power up, the switching phase of all

regulators is defaulted to 0 degrees and can be modified during the system On state.

Table 40. SWx phase configuration

SWx_PHASE[2:0]

Phase shift [degrees]

000

001

010

135

011

180

100

225

101

270

110

315

111

0 (default)

Each one of the buck regulator provides 2 OTP bits to configure the value of the inductor

used in the corresponding block. The OTP_SWx_LSELECT[1:0] allows to choose the

inductor as shown in Table 41.

Table 41. SWx inductor selection bits

OTP_SWx_LSELECT[1:0]

Inductor value

1.0 µH

0.47 µH

1.5 µH

Reserved

15.2.1 SW2 VTT operation

SW2 features a selectable VTT mode to create VTT termination for DDR memories.

When SW2_VTTEN = 1, the VTT mode is enabled. In this mode, SW2 reference voltage

is internally connected to SW1FB output through a divider by 2.

During the VTT mode, the DVS operation on SW2 is disabled and SW2 output is given

by VSW1FB / 2. In this mode, the minimum output voltage configuration for SW1 should be

800 mV to ensure the SW2 is still within the regulation range at its output.

During the power up sequence, the SW2 (VTT) may be turned on in the same or at a slot

higher than SW1, as required by the system. When SW2 and SW1 are enabled in the

same slot, SW2 will always track the VSW1/2. When SW2 is enabled after SW1, it will

ramp up gradually to a predefined voltage and once this voltage is reached, it will start

tracking VSW1/2. The user may adjust the value at which the SW2 should start tracking

the voltage on the SW1 regulator by setting the OTP_VSW2 register accordingly.

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