MPF5024AMBA0ES datasheet(81/93 Pages) NXP

81 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

81 / 93

ADDR

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Configuration

OTP DEBUG1

BG Monitor Disabled

OTP SW COMP1

SW2 = 65GM | SW1 = 65GM

OTP SW COMP2

SW4 = 65GM | SW3 = 65GM

18 Functional safety

18.1 System safety strategy

The PF5024 is defined in a context of safety and shall provide a set of features to

achieve the safety goals on such context. It provides a flexible yet complete safety

architecture to comply with ASIL B systems providing full programmability to enable

or disable features to address the safety goal. This architecture includes protective

mechanisms to avoid unwanted modification on the respective safety features, as

required by the system.

The following are features considered to be critical for the functional safety strategy:

• Internal watchdog timer

• External watchdog monitoring input (WDI)

• Output voltage monitoring with dedicated bandgap reference

• Protected I2C protocol with CRC verification

• Input overvoltage protection

• Analog built-in self-test (ABIST)

18.2 Output voltage monitoring with dedicated bandgap reference

For the type 1 buck regulators, the OV/UV monitor operate from the same reference

as the regulator. To ensure the integrity of the type 1 buck regulators, a comparison

between the regulator bandgap and the monitoring bandgap is performed. A 5 % to

12 % difference between the two bandgaps is an indicator of a potential regulation or

monitoring fault and is considered as a critical issue. Therefore, the device prevents the

switching regulators from powering up.

On the PF5024 ASIL B device, if a bandgap error is detected during a power up event,

the self-test will fail and prevent the device from powering up regardless of the value of

the OTP_BGMON_BYPASS bit.

During system On state, if a drift between two bandgaps is detected:

• When OTP_BGMON_BYPASS = 0, the power stage of the voltage regulators will be

shutdown.

• When OTP_BGMON_BYPASS = 1, The bandgap monitor only sends an interrupt to

the system to announce the bandgap failure.

The BGMON_I is asserted when a bandgap failure occurs, provided it is not masked.

The BGMON_S bit is set to 0 when the bandgaps are within range, and set to 1 when the

bandgaps are out of range.

MPF5024AMBA0ES Datasheet(PDF) 81 Page - NXP Semiconductors

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