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MPF5024AMBA0ES Datasheet(PDF) 71 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 71 / 93 • EMREV (Address 0x02): contains the MSB bits PROG_ID[8:11] • PROG_ID (Address 0x03): contains the LSB bit PROG_ID[7:0] 16.1 PF5024 OTP mirror register map Reset types OFF_OTP Register loads the OTP mirror register values during power up OTP Register available in OTP bank only, Reset From fuses when VIN crosses UVDET threshold MR ADDR FUSE ADDR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 A0 0 OTP I2C — — — OTP_I2C_ SECURE_EN OTP_I2C_CRC_EN OTP_I2C_ADD[2:0] A1 1 OTP CTRL1 — — OTP_EWARN_TIME[1:0] OTP_FS_BYPASS OTP_STANDBYINV OTP_PG_ACTIVE OTP_PG_CHECK A2 2 OTP CTRL2 OTP_FSS_EN OTP_FSS_RANGE — OTP_XFAILB_EN OTP_VIN_OVLO_ SDWN OTP_VIN_OVLO_ EN OTP_VIN_OVLO_DBNC[1:0] A3 3 OTP CTRL3 OTP_VTT_PDOWN OTP_SW2_VTTEN — — OTP_SW4CONFIG[1:0] OTP_SW1CONFIG[1:0] A4 4 OTP FREQ CTRL OTP_SW_MODE OTP_SYNC_MODE OTP_SYNCOUT_ EN OTP_FSYNC_ RANGE OTP_CLK_FREQ[3:0] A5 5 OTP PWRON — — OTP_PWRON_ MODE OTP_PWRON_DBNC[1:0] OTP_PWRON_ RST_EN OTP_TRESET[1:0] A6 6 OTP WD CONFIG — — OTP_WDI_MODE OTP_WDI_INV OTP_WD_EN OTP_ WD_STBY_ EN OTP_WDI_STBY_ ACTIVE OTP_WDWINDOW A7 7 OTP WD EXPIRE — — — — — OTP_WD_MAX_EXPIRE[2:0] A8 8 OTP WD COUNTER OTP_WD_DURATION[3:0] OTP_WD_MAX_CNT [3:0] A9 9 OTP FAULT COUNTERS OTP_FS_MAX_CNT[3:0] OTP_FAULT_MAX_CNT[3:0] AA A OTP FAULT TIMERS — OTP_FS_OK_TIMER[2:0] OTP_TIMER_FAULT[3:0] AB B OTP PWRDN DLY1 OTP_GRP4_DLY[1:0] OTP_GRP3_DLY[1:0] OTP_GRP2_DLY[1:0] OTP_GRP1_DLY[1:0] AC C OTP PWRDN DLY2 OTP_PD_SEQ_DLY[1:0] — — — — OTP_RESETBMCU_DLY[1:0] AD D OTP PWRUP CTRL — OTP_PWRDWN_ MODE OTP_PGOOD_PDGRP[1:0] OTP_RESETBMCU_PDGRP[1:0] OTP_SEQ_TBASE[1:0] AE E OTP RESETBMCU PWRUP OTP_RESETBMCU_SEQ[7:0] AF F OTP PGOOD PWRUP OTP_PGOOD_SEQ[7:0] B0 10 OTP SW1 VOLT OTP_VSW1[7:0] B1 11 OTP SW1 PWRUP OTP_SW1_SEQ[7:0] B2 12 OTP SW1 CONFIG1 OTP_SW1UV_TH[1:0] OTP_SW1OV_TH[1:0] OTP_SW1_PDGRP[1:0] OTP_SW1ILIM[1:0] B3 13 OTP SW1 CONFIG2 OTP_SW1_LSELECT[1:0] OTP_SW1PHASE[2:0] — OTP_SW1_PG_EN OTP_SW1_ WDBYPASS B4 14 OTP SW2 VOLT OTP_VSW2[7:0] B5 15 OTP SW2 PWRUP OTP_SW2_SEQ[7:0] B6 16 OTP SW2 CONFIG1 OTP_SW2UV_TH[1:0] OTP_SW2OV_TH[1:0] OTP_SW2_PDGRP[1:0] OTP_SW2ILIM[1:0] B7 17 OTP SW2 CONFIG2 OTP_SW2_LSELECT[1:0] OTP_SW2PHASE[2:0] — OTP_SW2_PG_EN OTP_SW2_ WDBYPASS B8 18 OTP SW3_ VOLT OTP_VSW3[7:0] B9 19 OTP SW3 PWRUP OTP_SW3_SEQ[7:0] BA 1A OTP SW3 CONFIG1 OTP_SW3UV_TH[1:0] OTP_SW3OV_TH[1:0] OTP_SW3_PDGRP[1:0] OTP_SW3ILIM[1:0] BB 1B OTP SW3 CONFIG2 OTP_SW3_LSELECT[1:0] OTP_SW3PHASE[2:0] — OTP_SW3_PG_EN OTP_SW3_ WDBYPASS BC 1C OTP SW4 VOLT OTP_VSW4[7:0] |
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