MPF5024AMBA0ES datasheet(60/93 Pages) NXP

60 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

60 / 93

aaa-028069

10.4 µs

5.2 µs

5 %

fosc

10 %

fosc

time

SS_RANGE = 0

SS_RANGE = 1

fmod = 24 kHz

time

Figure 26. Spread-spectrum waveforms

If the frequency spread-spectrum is enabled, the switching regulators should be set in

PWM mode to ensure clock synchronization at all time.

If the external clock synchronization is enabled, (SYNC_MODE = 1), the spread

spectrum is disabled regardless of the value of the FSS_EN bit.

15.4.5 Clock synchronization

An external clock can be fed via the SYNC pin to synchronize the switching regulators to

this external clock.

When the OTP_SYNC_MODE = 0, the external clock synchronization is disabled. In this

case, the PLL is disabled, and the device always uses the internal high frequency clock

to generate the main frequency for the switching regulators.

When the OTP_SYNC_MODE = 1, the external clock synchronization is enabled. In this

case, the internal PLL is always enabled and it uses either the internal high frequency

clock or the SYNC pin as the source to generate the main frequency for the switching

regulators.

If the SYNCIN function is not used, the pin should be grounded. If the external clock is

meant to start up after the PMIC has started, the SYNC pin must be maintained low until

the external clock is applied.

The SYNC pin is prepared to detect clock signals with a 1.8 V or 3.3 V amplitude and

within the frequency range set by the FSYNC_RANGE bit.

MPF5024AMBA0ES Datasheet(PDF) 60 Page - NXP Semiconductors