MPF5024AMBA0ES datasheet(76/93 Pages) NXP

76 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

76 / 93

test a custom power up configuration and/or burn the configuration into the OTP fuses to

generate a customized default power up configuration.

When VDDOTP = V1P5D, the I2C functional register will always be loaded from the

hardwire configuration each time a default loading is required. Therefore, no TBB

operation is possible in this configuration.

In the event of a TRIM/OTP loading failure or a self-test failure, the corresponding fault

flag is set and any PWRUP event is ignored until the flags are cleared by writing a 1

during the QPU_OFF state.

The TRIM_NOK, OTP_NOK and STEST_NOK flags can only be written when the

TBBEN = V1P5D (in TBB mode). In normal operation, the TRIM_NOK, OTP_NOK and

STEST_NOK flags can only be read, but not cleared.

17.1 TBB (Try Before Buy) operation

The PF5024 allows temporary configuration (TBB) to debug or test a customized power

up configuration in the system. In order to access the TBB mode, the TBBEN pin should

be pulled up to V1P5D.

In this mode of operation, the device ignores the default value of the LPM_OFF bit and

moves into the QPU_Off state, regardless of the result of the self-test. However, the

actual result of the self-test is notified by the STEST_NOK flag.

• When the self-test is successful the STEST_NOK flag is set to 0.

• When the self-test has failed, the STEST_NOK flag is set to 1.

In the TBB mode, the following conditions are valid:

• I2C communication uses standard communication with no CRC and secure write

disabled.

• Default I2C address is 0x08 regardless of the address configured by OTP.

• Watchdog monitoring is disabled (including WDI and internal watchdog timer).

• The PF5024 can communicate through I2C as long as VDDIO is provided to the PMIC

externally.

The PAGE[2:0] bits are provided to grant access to the mirror registers and other OTP

dedicated bits. When the device is in the TBB mode, it can access the mirror registers

in the extended register Page 1. With the TBBEN pin pulled low, access to the extended

The mirror registers are preloaded with the values from the OTP configuration. These

may be modified to set the proper power up configuration during TBB operation.

If a power up event is present with the TBBEN pin pulled to V1P5D, the device will power

up with the proper configuration but limited functionality.

Limited functionality includes:

• Default I2C address = 0x08

• CRC and secure write disabled

• Watchdog operation/monitoring disable

In order to allow TBB operation with full functionality, the TBBEN pin must be low when

the power up event occurs.

MPF5024AMBA0ES Datasheet(PDF) 76 Page - NXP Semiconductors

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