MPF5024AMBA0ES datasheet(26/93 Pages) NXP

Part #	MPF5024AMBA0ES

Description	Power management integrated circuit (PMIC) for high performance applications

PDF	93 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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26 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

26 / 93

aaa-030049

120 µs

GRP3_DLY

120 µs

GRP2_DLY

120 µs

GRP1_DLY

10 µs

PWRON

PDWN_GRP1

GPR1_DLY = 120 µs

SW1

SW4

RESETBMCU_DLY = 10 µS

PDWN_GRP2

GPR2_DLY = 120 µs

SW2

PDWN_GRP3

GPR3_DLY = 120 µs

SW3

PDWN_GRP4

SW2

SW3

SW4

RESETBMCU

SW1

Figure 10. Group power down sequence example

14.6.2.3 Power down delay

After a power down sequence is started, the PWRON pin shall be masked until the

sequence is finished and the programmable power down delay is reached. The device

can power up again if a power up event is present. The power down delay time can be

programmed on an OTP via the OTP_PD_SEQ_DLY[1:0] bits.

Table 22. Power down delay selection

OTP_PD_SEQ_DLY[1:0]

Delay after power down sequence

No delay

1.5 ms

5.0 ms

10 ms

MPF5024AMBA0ES Datasheet(PDF) 26 Page - NXP Semiconductors

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