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MPF5024AMBA0ES Datasheet(PDF) 61 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 93 page ![]() NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 61 / 93 • When the FSYNC_RANGE = 0, the input frequency range at SYNC pin should be between 2000 kHz and 3000 kHz. • When the FSYNC_RANGE = 1, the input frequency range at SYNC pin should be between 333 kHz and 500 kHz. The OTP_FSYNC_RANGE bit is used to select the default frequency range accepted in the SYNC pin. The external clock duty cycle at the SYNC pin should be between 40 % and 60 %. An input frequency in the SYNC pin outside the range defined by the FSYNC_RANGE bit is detected as invalid. If the external clock is not present or invalid, the device automatically switches to the internal clock and sets the FSYNC_FLT_I interrupt, which in turn asserts the INTB pin provided it is not masked. The FSYNC_FLT_S bit is set to 1 as long as the input frequency is not preset or invalid, and it is cleared to 0 when the SYNC has a valid input frequency. The device switches back to the external switching frequency only when both, the FSYNC_FLT_I interrupt has been cleared and the SYNC pin sees a valid frequency. When the external clock is selected, the switching regulators should be set in PWM mode to ensure clock synchronization at all time. When the OTP_SYNC_MODE = 0 and OTP_SYNCOUT_EN = 1, the SYNC pin is used to synchronize an external device to the PF5024. The SYNC pin outputs the main frequency used for the switching regulators in the range of 2.0 MHz to 3.0 MHz. The SYNCOUT_EN bit can be used to enable or disable the SYNCOUT feature via I2C during the system On state. • When SYNCOUT_EN = 0, the SYNCOUT feature is disabled and the pin is internally pulled to ground. • When SYNCOUT_EN = 1, the SYNC pin toggles at the base frequency used by the switching regulators. The SYNCOUT function can be enabled or disabled by default by using the OTP_SYNCOUT_EN bit. Table 52. Clock management specifications All parameters are specified at TA = −40 to 125 °C, unless otherwise noted. Typical values are characterized at VIN = 5.0 V and TA = 25 °C, unless otherwise noted. Symbol Parameter Min Typ Max Unit Low frequency clock IQ100KHz 100 kHz clock quiescent current — — 3.0 µA f100KHzACC 100 kHz clock accuracy −5.0 — 5.0 % High frequency clock f20MHz High frequency clock nominal frequency via CLK_FREQ[3:0] = 0000 — 20 — MHz f20MzACC High frequency clock accuracy −6.0 — 6.0 % t20MHzStep Clock step transition time Minimum time to transition from one frequency step to the next in manual tuning mode — 5.2 — µs FSSRANGE Spread-spectrum range FSS_RANGE= 0 via CLK_FREQ[3:0] Spread-spectrum is done around center frequency of 20 MHz — ±5.0 — % |
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