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MPF5024AMBA0ES Datasheet(PDF) 58 Page - NXP Semiconductors |
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MPF5024AMBA0ES Datasheet(HTML) 58 Page - NXP Semiconductors |
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58 / 93 page ![]() NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 58 / 93 aaa-033243 DIVIDE BY 1 OR 6 INTERNAL OSCILLATOR 20 MHz ± 20 % 16 to 24 MHz SYNC 333 to 500 kHz or 2 - 3 MHz 16 to 24 MHz 16 to 24 MHz 16 to 24 MHz CLOCK MANAGEMENT BLOCK 416.67 kHz 333 kHz - 500 kHz 333 kHz - 500 kHz En OUT f1 f1 + 45° f1 + 90° f1 + 135° f1 + 180° f1 + 225° f1 + 270° f1 + 315° IN centered DIVIDE BY 48 FREQUENCY WATCHDOG INTERNAL OSCILLATOR 100 kHz ± 5 % FSS_EN FSS_RANGE CKL_FRQ[3:0] FSYNC_RANGE SYNC_MODE 100 kHz system clock MUX 0 1 MUX 0 1 SYNCOUT_EN PLL X48 DIV 1 BY 8 DLY DLY DLY DLY DLY DLY DLY DLY I/O SYNCOUT Figure 25. Clock management architecture 15.4.1 Low frequency clock A low power 100 kHz clock is provided for overall logic and digital control. Internal logic and debounce timers are based on this 100 kHz clock. 15.4.2 High frequency clock The PF5024 features a high frequency clock with nominal frequency of 20 MHz. Clock frequency is programmable over a range of ±20 % via the CLK_FREQ[3:0] control bits. 15.4.3 Manual frequency tuning The PF5024 features a manual frequency tuning to set the switching frequency of the high frequency clock. The CLK_FREQ [3:0] bits allow a manual frequency tuning of the high frequency clock from 16 MHz to 24 MHz. If a frequency change of two or more steps is requested by a single I2C command, the device performs a gradual frequency change passing through all steps in between with a 5.2 µs time between each frequency step. When the frequency reaches the programmed value, The FREQ_RDY_I asserts the INTB pin, provided it is not masked. When the internal clock is used as the main frequency for the power generation, an internal frequency divider by 8 is used to generate the switching frequency for all the buck regulators. Adjusting the frequency of the high frequency clock allows for manual tuning of the switching frequencies for the buck regulators from 2.0 MHz to 3.0 MHz. |
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