MPF5024AMBA0ES datasheet(57/93 Pages) NXP

57 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

57 / 93

15.3.1 Electrical characteristics

Table 50. VMON electrical characteristics

All parameters are specified at TA = –40 °C to 125 °C, unless otherwise noted. Typical values are characterized at VIN =

5.0 V, VxFB = 1.5 V (Type 1 Buck regulator), and TA = 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

IQON

Block quiescent current, when block is enabled one block

per regulator

one block per regulator

—

µA

IOFF

Block leakage current when disabled

—

500

tON_MON

Voltage monitor settling time after enabled

—

µs

VxFBUVHysteresis

Power good (UV) hysteresis

Voltage difference between UV rising and falling

thresholds

—

0.5

—

VUV_Tol

Undervoltage falling threshold accuracy

With respect to target feedback voltage tolerance

For type 1 switching regulator when VSWxFB > 0.75 V

−2

—

VUV_Tol

Under voltage falling threshold accuracy

With respect to target feedback voltage

For type 1 switching regulator when VSWxFB ≤ 0.75 V

−3

—

Power good (UV) debounce time UV_DV = 00

2.5

5.0

7.5

Power good (UV) debounce time UV_DV = 01

Power good (UV) debounce time UV_DV = 10

tUV_DB

Power good (UV) debounce time UV_DV = 11

µs

VOV_Tol

Overvoltage rising threshold accuracy

With respect to target feedback voltage tolerance

For type 1 switching regulator when VSWxFB > 0.75 V

−2

—

VOV_Tol

Overvoltage rising threshold

With respect to target feedback voltage tolerance

For type 1 switching regulator when VSWxFB ≤ 0.75 V

−3

—

VxFBOVHysteresis

Overvoltage (OV) hysteresis

Voltage difference between OV rising and falling

thresholds

—

0.5

—

Power good (OV) debounce time OV_DV = 00

Power good (OV) debounce time OV_DV = 01

Power good (OV) debounce time OV_DV = 10

105

tOV_DB

Power good (OV) debounce time OV_DV = 11

135

160

µs

15.4 Clock management

The clock management provides a top-level management control scheme of internal

clock and external synchronization intended to be primarily used for the switching

regulators. The clock management incorporates various subblocks:

• Low power 100 kHz clock

• Internal high frequency clock with programmable frequency

• Phase Locked Loop (PLL)

A digital clock management interface is in charge of supporting interaction among these

blocks.

The clock management provides clocking signals for the internal state machine, the

switching frequencies for the buck converters as well as the multiples of those switching

frequencies in order to enable phase shifting for multiple phase operation.

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