MPF5024AMBA0ES datasheet(24/93 Pages) NXP

24 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

24 / 93

4. When Tj crosses the thermal shutdown threshold as the temperature rises.

When the PF5024 experiences a turn off event due to a hard fault condition, the device

pass through the fail-safe transition after regulators have been powered down.

14.6.2 Power down sequencing

During a power down sequence, output voltage regulators can be turned off in two

different modes as defined by the PWRDWN_MODE bit.

1. When PWRDWN_MODE = 0, the regulators power down in sequential mode.

2. When PWRDWN_MODE = 1, the regulators power down by groups.

During transition from run to standby, the power down sequencer is activated in the

corresponding mode, if any of the external regulators are turned off in the standby

configuration. If external regulators are not turned off during this transition, the power

down sequencer is bypassed and the transition happens at once (any associated DVS

transitions could still take time).

The PWRDN_I interrupt is set at the end of the transition from run to standby when the

last regulator has reached its final state, even if external regulators are not turned off

during this transition.

14.6.2.1 Sequential power down

When the device is set to the sequential power down, it uses the same _SEQ[7:0]

registers as the power up sequence to power down in reverse order.

All regulators with the _SEQ[7:0] bits set to 0x00, power down immediately and the

remaining regulators power down one OTP_SEQ_TBASE[1:0] delay after, in reverse

order as defined in the _SEQ[7:0] bits.

If PGOOD pin is used as a GPO, it is de-asserted as part of the power down sequence

as indicated by the PGOOD_SEQ[7:0] bits.

If the MCU requires a different power down sequence, it can change the values of the

SEQ_TBASE[1:0] and the _SEQ[7:0] bits during the system On state.

When the state machine passes through any of the Off modes, the contents of the

SEQ_TBASE[1:0] and _SEQ[7:0] bits are reloaded with the corresponding mirror register

(OTP) values before it starts the next power up sequence.

14.6.2.2 Group power down

When the device is configured to power down in groups, the regulators are assigned to a

specific power down group. All regulators assigned to the same group are disabled at the

same time when the corresponding group is due to be disabled.

Power down groups shut down in decreasing order starting from the lowest hierarchy

group with a regulator shutting down (for instance Group 4 being the lowest hierarchy

and Group 1 the highest hierarchy group). If no regulators are set to the lowest hierarchy

group, the power down sequence timer starts off the next available group that contains a

regulator to power down.

Each regulator has its own _PDGRP[1:0] bits to set the power down group it belongs to

as shown in Table 19.

MPF5024AMBA0ES Datasheet(PDF) 24 Page - NXP Semiconductors

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