MPF5024AMBA0ES datasheet(40/93 Pages) NXP

40 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

40 / 93

• When WDI_MODE = 0, a WDI asserted performs a soft WD reset.

The default value of the WDI_MODE bit is set by the OTP _WDI_MODE bit in the OTP

The WDI_STBY_ACTIVE bit allows the WDI pin to generate a watchdog event during the

standby state.

• When WDI_STBY_ACTIVE = 0, asserting the WDI will not generate a watchdog event

during the standby state.

• When WDI_STBY_ACTIVE = 1, asserting the WDI will start a watchdog event during

the standby state.

The OTP_WDI_STBY_ACTIVE is used to configure whether the WDI is active in the

standby state or not by default upon power up.

See Section 15.7 "Watchdog event management" for details on watchdog event.

14.9.6 PGOOD

PGOOD is an open drain output programmable as a power good indicator pin or GPO. In

the application, PGOOD can be pulled up to VDDIO with a 100 kΩ resistor.

When OTP_PG_ACTIVE = 0, the PGOOD pin is used as a general purpose output.

As a GPO, during the run state, the state of the pin is controlled by the RUN_PG_GPO

bit in the functional I2C registers:

• When RUN_PG_GPO = 1, the PGOOD pin is high

• When RUN_PG_GPO = 0, the PGOOD pin is low

During the standby state, the state of the pin is controlled by the STBY_PG_GPO bit in

the functional I2C registers:

• When STBY_PG_GPO = 1, the PGOOD pin is high

• When STBY_PG_GPO = 0, the PGOOD pin is low

When used as a GPO, the PGOOD pin can be enabled high as part of the

power up sequence as programmed by the OTP_SEQ_TBASE[1:0] and the

OTP_PGOOD_SEQ[7:0] bits. If enabled as part of the power up sequence, both the

RUN_PG_GPO and STBY_PG_GPO bits are loaded with 1, otherwise they are loaded

with 0 upon power up.

When OTP_PG_ACTIVE = 1, the PGOOD pin is in Power good (PG) mode and it acts as

a PGOOD indicator for the selected output voltages in the PF5024.

There is an individual PG monitor for every regulator. Each monitor provides an internal

PG signal that can be selected to control the status of the PGOOD pin upon an OV or UV

condition when the corresponding SWxPG_EN bit is set. The status of the PGOOD pin is

a logic AND function of the internal PG signals of the selected monitors.

• When the PG_EN = 1, the corresponding regulator becomes part of the AND function

that controls the PGOOD pin.

• When the PG_EN = 0, the corresponding regulator does not control the status of the

PGOOD pin.

The PGOOD pin is pulled low when any of the selected regulator outputs falls above

or below the programmed OV/UV thresholds and the corresponding OV/UV interrupt is

generated. If the faulty condition is removed, the corresponding OV_S/UV_S bit goes low

MPF5024AMBA0ES Datasheet(PDF) 40 Page - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 40 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL