MPF5024AMBA0ES datasheet(41/93 Pages) NXP

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NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

41 / 93

to indicate the output is back in regulation, however, the interrupt remains latched until it

is cleared.

The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt

registers. For more details on handling interrupts, see Section 14.8 "Interrupt

management".

When a particular regulator is disabled (via OTP, or I2C, or by change in state of PMIC

such as going to standby mode), it no longer controls the PGOOD pin.

In the Off mode and during the power up sequence, the PGOOD pin is held low until

RESETBMCU is ready to be released, at this point, the PG monitors are unmasked and

the PGOOD pin is released high if all the internal PG monitors are in regulation. In the

event that one or more outputs are not in regulation by the time RESETBMCU is ready to

de-assert, the PGOOD pin is held low and the PF5024 performs the corresponding fault

protection mechanism as described in Section 14.7.1 "Fault monitoring during power up

state".

14.9.7 PGOODx

The PGOODx pins are open drain outputs to provide the power good status of each

regulator. In the application, PGOODx can be pulled up to VDDIO with a 100 kΩ resistor.

The PGOODx pin is pulled low when the corresponding regulator output falls above or

below the programmed OV/UV thresholds.

The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt

registers. For more details on handling interrupts, see Section 14.8 "Interrupt

management".

Table 31. PGOODx assignment

PF5024 regulator

PGOOD1

SW1

PGOOD2

SW2

PGOOD3

SW3

PGOOD4

SW4

14.9.8 ENx

The ENx input pin is used to enable or disable the dedicated regulator via hardware.

When the ENx pin is asserted high, the corresponding regulator is controlled by

SWx_RUN_MODE.

When the ENx pin is asserted low, the corresponding regulator is turned off.

Table 32. ENx assignment

PF5024 regulator

EN1

SW1

EN2

SW2

EN3

SW3

EN4

SW4

The status of the ENx pin can be monitored via the corresponding ENx_S flag bit in the

EN SENSE register.

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