MPF5024AMBA0ES datasheet(12/93 Pages) NXP

12 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

12 / 93

Symbol

Description

Conditions

Transition R

Self-test to fail-safe transition

1. Self-tests fail 3 times

&& TBBEN = low

Transition S

Power down (fault) to fail-safe transition Turn off event due to a fault condition moves to fail-safe transition

1. Power down sequence is finished

1. FS_CNT < FS_MAX_CNT

Transition U

Fail-safe transition to LP_Off

2. OTP_FS_BYPASS = 1

Transition P

Fail-safe transition to fail-safe state

(PF5024 ASIL B only)

1. FS_CNT = FS_MAX_CNT

&& OTP_FS_BYPASS = 0

13.1 State descriptions

13.1.1 OTP/TRIM load

Upon VIN application, the V1P5D and V1P5A regulators are turned on automatically.

Once the V1P5D and V1P5A cross their respective POR thresholds, the fuses (for trim

and OTP) are loaded into the mirror registers and into the functional I2C registers if

configured by the voltage on the VDDOTP pin.

The fuse circuits have a CRC error check routine which reports and protects against

corresponding TRIM_NOK or OTP_NOK flag is asserted. See Section 17 "OTP/TBB and

hardwire default configurations" for details on handling fuse load errors.

If no fuse load errors are present, the state machine moves to the LP_off state.

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during the

system On mode. By default, the LPM_OFF = 0 when VIN crosses the UVDET threshold,

therefore the state machine stops at the LP_Off state until a valid power up event

is present. When LPM_OFF = 1, the state machine transitions automatically to the

QPU_Off state if no power up event has been present and waits in the QPU_Off until a

valid power up event is present.

The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current

(stay in the LP_Off state) or quick power up (move to the QPU_Off state).

If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error

is detected, the PF5024 ignores the power up event and remains in the LP_Off state to

avoid any potential damage to the system.

13.1.3 Self-test routine (PF5024 ASIL B only)

When the device transitions from the LP_Off state, it turns on all necessary internal

circuits as it moves into the self-test routine and performs a self-check routine to verify

the integrity of the internal circuits.

During the self-test routine the following blocks are verified:

• The high speed clock circuit is operating within a maximum of 15 % tolerance

• The output of both the voltage generation bandgap and the monitoring bandgap are not

more than 5 % to 12 % apart from each other

MPF5024AMBA0ES Datasheet(PDF) 12 Page - NXP Semiconductors

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